Patent US5329167A successfully refreshed from Google Patents.
US5329167A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Test flip-flop with an auxillary latch enabling two (2) bits of storage
Assignee: Raytheon Co
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Filing: 1992-09-25
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Granted: 1994-07-12
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Expires: 2012-09-25
Abstract
Abstract A scan flip-flop cell including a flip-flop, a feed-back path by which the output of the flip-flop can be controllably held, and a latch in the feedback path that allows the cell to store two bits of data simultaneously.
Inventors
- 👤 William D. Farwell
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-10 01:26
CPC Classifications
G; G01; G01R; G01R31/00; G01R31/28; G01R31/317; G01R31/3181; G01R31/3185; G01R31/318533; G01R31/318541; H; H03; H03K; H03K3/00; H03K3/02; H03K3/027; H03K3/037; H03K3/0375
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
243 words
A scan flip-flop cell for receiving a serial scan input and a data input, and for providing a serial scan output and a data output, comprising: a flip-flop having an input and an output, wherein said flip-flop output provides the data output of the scan flip-flop cell; delay means for providing a delayed replica of the output of said flip-flop, said delayed replica comprising the serial scan output of the scan flip-flop cell; latching means responsive to said delayed replica of the flip-flop output for selectively latching said delayed replica pursuant to a latch control signal; first selection means responsive to the serial scan input to the scan flip-flop cell, the output of said latching means, and said delayed replica of the flip-flop output for providing an output which is a replica of (a) the serial scan input, (b) said latch output, or (c) said replica of the flip-flop output as selected by first and second control signals; second selection means responsive to the data input for the scan flip-flop cell and the output of said first selection means for providing an output which is a replica of (a) the first selection means output or (b) the data input to the scan flip-flop cell as selected by a third control signal, the output of said second selection means being provided to the input of said flip-flop such that the input to said flip-flop is selected by said first, second, and third control signals.
Claim 2
Dependent Claim
243 words
A scan flip-flop cell for receiving a serial scan input and a data input, and for providing a serial scan output and a data output, comprising: a flip-flop having an input and an output, wherein said flip-flop output provides the data output of the scan flip-flop cell; delay means for providing a delayed replica of the output of said flip-flop, said delayed replica comprising the serial scan output of the scan flip-flop cell; latching means responsive to said delayed replica of the flip-flop output for selectively latching said delayed replica pursuant to a latch control signal; first selection means responsive to the serial scan input to the scan flip-flop cell, the output of said latching means, and said delayed replica of the flip-flop output for providing an output which is a replica of (a) the serial scan input, (b) said latch output, or (c) said replica of the flip-flop output as selected by first and second control signals; second selection means responsive to the data input for the scan flip-flop cell and the output of said first selection means for providing an output which is a replica of (a) the first selection means output or (b) the data input to the scan flip-flop cell as selected by a third control signal, the output of said second selection means being provided to the input of said flip-flop such that the input to said flip-flop is selected by said first, second, and third control signals.
Claim 3
Dependent Claim
18 words
The scan flip-flop cell of claim 1 wherein said delay means comprises first and second serially connected inverters.
Claim 4
Dependent Claim
25 words
The scan flip-flop cell of claim 2 further including gating means responsive to the first and second control signals for providing the third control signal.
Claim 5
Dependent Claim
289 words
A scan flip-flop cell for receiving a serial scan input and a data input, and for providing a serial scan output and a data output, comprising: a flip-flop having an input and an output, wherein said flip-flop output provides the data output of the scan flip-flop cell; delay means for providing a delayed replica of the output of said flip-flop, said delayed replica comprising the serial scan output of the scan flip-flop cell; latching means responsive to said delayed replica of the flip-flop output for selectively latching said delayed replica pursuant to a latch control signal; first multiplexing means responsive to the serial scan input to the scan flip-flop cell and to the output of said latching means for providing an output which is a replica of (a) the serial scan input or (b) said latch output as selected by a first multiplexing control signal; second multiplexing means responsive to said delayed replica of the flip-flop output and to the output of said first multiplexing means for providing an output which is a replica of (a) said delayed replica of the flip-flop output or (b) the output of said first multiplexing means as selected by a second multiplexing control signal; and third multiplexing means responsive to the data input for the scan flip-flop cell and the output of said second multiplexing means for providing an output which is a replica of (a) the data input for the scan flip-flop cell or (b) the output of said second multiplexing means as selected by a third multiplexing control signal, the output of said third multiplexing means being provided to the input of said flip-flop such that the input to said flip-flop is selected by the first, second, and third control signals.
Claim 6
Dependent Claim
289 words
A scan flip-flop cell for receiving a serial scan input and a data input, and for providing a serial scan output and a data output, comprising: a flip-flop having an input and an output, wherein said flip-flop output provides the data output of the scan flip-flop cell; delay means for providing a delayed replica of the output of said flip-flop, said delayed replica comprising the serial scan output of the scan flip-flop cell; latching means responsive to said delayed replica of the flip-flop output for selectively latching said delayed replica pursuant to a latch control signal; first multiplexing means responsive to the serial scan input to the scan flip-flop cell and to the output of said latching means for providing an output which is a replica of (a) the serial scan input or (b) said latch output as selected by a first multiplexing control signal; second multiplexing means responsive to said delayed replica of the flip-flop output and to the output of said first multiplexing means for providing an output which is a replica of (a) said delayed replica of the flip-flop output or (b) the output of said first multiplexing means as selected by a second multiplexing control signal; and third multiplexing means responsive to the data input for the scan flip-flop cell and the output of said second multiplexing means for providing an output which is a replica of (a) the data input for the scan flip-flop cell or (b) the output of said second multiplexing means as selected by a third multiplexing control signal, the output of said third multiplexing means being provided to the input of said flip-flop such that the input to said flip-flop is selected by the first, second, and third control signals.
Claim 7
Dependent Claim
18 words
The scan flip-flop cell of claim 4 wherein said delay means comprises first and second serially connected inverters.
Claim 8
Dependent Claim
27 words
The scan flip-flop cell of claim 5 further including gating means responsive to the first and second multiplexing control signal for providing the third multiplexing control signal.
References Cited (Backward Citations)
US4697279A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1997-07-11 | 1998-01-10 | 1998-07-12 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-07-11 | 2002-01-10 | 2002-07-12 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-07-11 | 2006-01-10 | 2006-07-12 | $7700.00 | Window Closed / Lapsed |