Process for fabricating lateral PNP transistor structure and BICMOS IC

Claim 1

A method of forming a lateral PNP transistor in a substrate of semiconductor material during a BICMOS process for fabricating bipolar NPN transistors and CMOS transistors including PMOS transistors and NMOS transistors in a BICMOS integrated circuit, said method comprising: forming a base N+ buried layer in the IC substrate to underlie a bipolar PNP transistor during an N type buried layer mask, etch and N type introduction sequence used to form a buried collector layer in the semiconductor material substrate to underlie NPN transistors of the BICMOS IC; forming a PNP base Retro NWELL and a PNP base contact Retro NWELL in the base N type buried layer to underlie the active base region and base contact region respectively of the bipolar PNP transistor during a Retro NWELL mask, etch and N type introduction sequence used to form Retro NWELLs in the IC substrate to underlie PMOS transistors of the BICMOS IC; growing an epitaxial layer in the range from undoped to low doped EPI across the IC substrate including the area for the PNP transistor; forming a PNP base contact N+ sink region over the base contact NWELL during a sink definition mask, etch and N type introduction sequence of the BICMOS process used to form an NPN collector sink region through the epitaxial layer to a buried collector layer for bipolar NPN transistors; separating the PNP base contact N+ sink region from a collector region of the PNP transistor by field oxide during an active area definition mask, etch and grow sequence of the BICMOS process used for framing CMOS transistors in field oxide and isolating PMOS and NMOS transistors with field oxide; forming the collector and emitter regions of the bipolar PNP transistor using at least one of an NPN base definition mask, etch and P type introduction sequence of the BICMOS process used to form a base region of bipolar NPN transistors, and a P+S/D mask definition, etch and P type introduction sequence of the BICMOS process used to form the source and drain of PMOS transistors and to enhance the base region of bipolar NPN transistors; and forming metal contacts to the collector, emitter and base contact regions of the PNP transistors; thereby forming the lateral PNP transistor using the steps of the BICMOS process for fabricating NPN and CMOS transistors without adding additional steps.

Claim 2

A method of forming a lateral PNP transistor in a substrate of semiconductor material during a BICMOS process for fabricating bipolar NPN transistors and CMOS transistors including PMOS transistors and NMOS transistors in a BICMOS integrated circuit, said method comprising: forming a base N+ buried layer in the IC substrate to underlie a bipolar PNP transistor during an N type buried layer mask, etch and N type introduction sequence used to form a buried collector layer in the semiconductor material substrate to underlie NPN transistors of the BICMOS IC; forming a PNP base Retro NWELL and a PNP base contact Retro NWELL in the base N type buried layer to underlie the active base region and base contact region respectively of the bipolar PNP transistor during a Retro NWELL mask, etch and N type introduction sequence used to form Retro NWELLs in the IC substrate to underlie PMOS transistors of the BICMOS IC; growing an epitaxial layer in the range from undoped to low doped EPI across the IC substrate including the area for the PNP transistor; forming a PNP base contact N+ sink region over the base contact NWELL during a sink definition mask, etch and N type introduction sequence of the BICMOS process used to form an NPN collector sink region through the epitaxial layer to a buried collector layer for bipolar NPN transistors; separating the PNP base contact N+ sink region from a collector region of the PNP transistor by field oxide during an active area definition mask, etch and grow sequence of the BICMOS process used for framing CMOS transistors in field oxide and isolating PMOS and NMOS transistors with field oxide; forming the collector and emitter regions of the bipolar PNP transistor using at least one of an NPN base definition mask, etch and P type introduction sequence of the BICMOS process used to form a base region of bipolar NPN transistors, and a P+S/D mask definition, etch and P type introduction sequence of the BICMOS process used to form the source and drain of PMOS transistors and to enhance the base region of bipolar NPN transistors; and forming metal contacts to the collector, emitter and base contact regions of the PNP transistors; thereby forming the lateral PNP transistor using the steps of the BICMOS process for fabricating NPN and CMOS transistors without adding additional steps.

Claim 11

A method of forming a lateral PNP transistor in a substrate of semiconductor material during a BICMOS process for fabricating bipolar NPN transistors and CMOS transistors including PMOS transistors and NMOS transistors in a BICMOS integrated circuit, said BICMOS process including an N type buried layer mask, etch and N type introduction sequence for forming a buried collector layer in a semiconductor material substrate to underlie bipolar NPN transistors of the BICMOS IC, a Retro NWELL mask, etch and N type introduction sequence for forming Retro NWELLs in the IC substrate to underlie PMOS transistors of the BICMOS IC, growing an epitaxial layer of semiconductor material over the IC substrate, a sink definition mask, etch and N type introduction sequence for forming a collector sink region through the epitaxial layer to the buried collector layer for bipolar NPN transistors, an active area definition or field oxide definition mask, etch, and grow sequence for framing CMOS transistors in field oxide and spacing PMOS and NMOS transistors with field oxide, depositing a uniform layer of polycrystalline semiconductor material over the BICMOS integrated circuit, a poly definition mask and etch sequence for forming poly gates over the CMOS transistors of the BICMOS IC, and NPN base definition mask, etch and P type sequence introduction sequence for forming the base region of bipolar NPN transistors of the BICMOS IC, a contact definition mask and etch sequence for removing the CVD nitride layer in the collector, base, and emitter contact areas of bipolar NPN transistors of the BICMOS IC and forming self aligned transistors masks across the bipolar NPN transistors, and NPN emitter definition mask, etch and N type introduction sequence for forming the emitter regions and enhancing the collector regions of bipolar NPN transistors of the BICMOS IC, and P+ source drain mask, etch and P type introduction sequence for forming the source and drain of PMOS transistors and enhancing the base region of bipolar NPN transistors, and further contact definition and metal definition mask, etch and deposition sequences for forming metal contacts and metal leads with the electrodes of the bipolar NPN and CMOS PMOS and NMOS transistors, said method comprising: forming a base N type buried layer in the IC substrate to underlie the bipolar PNP transistor during the N+BL mask, etch and N type introduction sequence; forming a PNP base Retro NWELL and a PNP base contact Retro NWELL in the base N type buried layer to underlie the active base region (B) and base contact region respectively of the bipolar PNP transistor using the Retro NWELL mask, etch and N type introduction sequence; growing an epitaxial layer in the range from undoped to low doped EPI across the IC substrate and forming retrograde concentrations of N type material upward from the respective B/NWELL and BC/NWELL into the epitaxial layer; forming a base contact N+ sink region over the base contact NWELL in the epitaxial layer using the sink definition mask, etch and N type introduction sequence; separating the base contact N+ sink region from a collector region of the PNP transistor by field oxide using the active area definition mask, etch and grow sequence; forming the collector and emitter regions of the bipolar PNP transistor using at least one of the NPN base definition mask, etch and P type introduction sequence or the PMOS P+S/D mask definition, etch and P type introduction sequence; and forming metal contacts to the collector, emitter and base contact regions of the PNP transistor; thereby forming the lateral PNP transistor using the steps of the BICMOS process for fabricating NPN and CMOS transistors without adding additional steps.

Claim 12

A method of forming a lateral PNP transistor in a substrate of semiconductor material during a BICMOS process for fabricating bipolar NPN transistors and CMOS transistors including PMOS transistors and NMOS transistors in a BICMOS integrated circuit, said BICMOS process including an N type buried layer mask, etch and N type introduction sequence for forming a buried collector layer in a semiconductor material substrate to underlie bipolar NPN transistors of the BICMOS IC, a Retro NWELL mask, etch and N type introduction sequence for forming Retro NWELLs in the IC substrate to underlie PMOS transistors of the BICMOS IC, growing an epitaxial layer of semiconductor material over the IC substrate, a sink definition mask, etch and N type introduction sequence for forming a collector sink region through the epitaxial layer to the buried collector layer for bipolar NPN transistors, an active area definition or field oxide definition mask, etch, and grow sequence for framing CMOS transistors in field oxide and spacing PMOS and NMOS transistors with field oxide, depositing a uniform layer of polycrystalline semiconductor material over the BICMOS integrated circuit, a poly definition mask and etch sequence for forming poly gates over the CMOS transistors of the BICMOS IC, and NPN base definition mask, etch and P type sequence introduction sequence for forming the base region of bipolar NPN transistors of the BICMOS IC, a contact definition mask and etch sequence for removing the CVD nitride layer in the collector, base, and emitter contact areas of bipolar NPN transistors of the BICMOS IC and forming self aligned transistors masks across the bipolar NPN transistors, and NPN emitter definition mask, etch and N type introduction sequence for forming the emitter regions and enhancing the collector regions of bipolar NPN transistors of the BICMOS IC, and P+ source drain mask, etch and P type introduction sequence for forming the source and drain of PMOS transistors and enhancing the base region of bipolar NPN transistors, and further contact definition and metal definition mask, etch and deposition sequences for forming metal contacts and metal leads with the electrodes of the bipolar NPN and CMOS PMOS and NMOS transistors, said method comprising: forming a base N type buried layer in the IC substrate to underlie the bipolar PNP transistor during the N+BL mask, etch and N type introduction sequence; forming a PNP base Retro NWELL and a PNP base contact Retro NWELL in the base N type buried layer to underlie the active base region (B) and base contact region respectively of the bipolar PNP transistor using the Retro NWELL mask, etch and N type introduction sequence; growing an epitaxial layer in the range from undoped to low doped EPI across the IC substrate and forming retrograde concentrations of N type material upward from the respective B/NWELL and BC/NWELL into the epitaxial layer; forming a base contact N+ sink region over the base contact NWELL in the epitaxial layer using the sink definition mask, etch and N type introduction sequence; separating the base contact N+ sink region from a collector region of the PNP transistor by field oxide using the active area definition mask, etch and grow sequence; forming the collector and emitter regions of the bipolar PNP transistor using at least one of the NPN base definition mask, etch and P type introduction sequence or the PMOS P+S/D mask definition, etch and P type introduction sequence; and forming metal contacts to the collector, emitter and base contact regions of the PNP transistor; thereby forming the lateral PNP transistor using the steps of the BICMOS process for fabricating NPN and CMOS transistors without adding additional steps.