Patent US197645A successfully refreshed from Google Patents.
Patent US5326709A successfully refreshed from Google Patents.
US5326709A
Expired / Lapsed
US
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Wafer testing process of a semiconductor device comprising a redundancy circuit
Assignee: Samsung Electronics Co Ltd
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Filing: 1992-12-18
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Granted: 1994-07-05
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Expires: 2012-12-18
Abstract
Abstract A wafer testing process of a semiconductor device provided with a redundancy circuit. The process comprises a step of removing a passivation film above a pad and link portion, pre-laser testing, laser-repairing, and final quality marking using an off-line inking method. Therefore, fabrication-test processes are simplified to one step by adopting the off-line inking method, thereby achieving productivity improvement, quality enhancement, and reduction of throughput time.
Inventors
- 👤 Hong-bae Moon
- 👤 Bon-youl Ku
- 👤 Gi-seung Song
- 👤 Tae-wook Seo
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 12:02
CPC Classifications
H; H10; H10P; H10P74/00; H10P74/23; H10P74/232; H10W; H10W46/00; H10W46/501; Y; Y10; Y10S; Y10S148/00; Y10S148/093
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
257 words
A testing process for a wafer containing a plurality of semiconductor chips, each chip having first and second passivation layers, redundancy circuits with program elements and pads for electrical connection thereto, comprising the steps of: (a) selectively removing a first passivation layer portion disposed over said pads of each said semiconductor chip to obtain a plurality of exposed pads and selectively removing a second passivation layer portion disposed over said program elements of each said semiconductor chip; (b) electrically testing every chip on said wafer through said exposed pads to identify defective chips on said wafer, including identification of defective but repairable chips and defective and unrepairable chips; (c) repairing said repairable chips by cutting said program elements on said repairable chips with a laser beam to obtain repaired chips; (d) testing a sample of said repairable chips after said laser repairing step to determine a representative goodness ratio of successfully repaired repairable chips versus unsuccessfully repaired repairable chips; (e) quality testing all of said repairable chips, identified in step (b) and which underwent laser repair in step (c), to determine which of said repairable chips were successfully repaired and which of said repairable chips were unsuccessfully repaired, if said goodness ratio is less than a threshold value, said step of quality testing all of said repairable chips being omitted if said goodness ratio is greater than or equal to said threshold value; and (f) quality marking each said defective unrepairable chip and each of said unsuccessfully repaired repairable chips as determined by said quality testing step.
Claim 2
Dependent Claim
257 words
A testing process for a wafer containing a plurality of semiconductor chips, each chip having first and second passivation layers, redundancy circuits with program elements and pads for electrical connection thereto, comprising the steps of: (a) selectively removing a first passivation layer portion disposed over said pads of each said semiconductor chip to obtain a plurality of exposed pads and selectively removing a second passivation layer portion disposed over said program elements of each said semiconductor chip; (b) electrically testing every chip on said wafer through said exposed pads to identify defective chips on said wafer, including identification of defective but repairable chips and defective and unrepairable chips; (c) repairing said repairable chips by cutting said program elements on said repairable chips with a laser beam to obtain repaired chips; (d) testing a sample of said repairable chips after said laser repairing step to determine a representative goodness ratio of successfully repaired repairable chips versus unsuccessfully repaired repairable chips; (e) quality testing all of said repairable chips, identified in step (b) and which underwent laser repair in step (c), to determine which of said repairable chips were successfully repaired and which of said repairable chips were unsuccessfully repaired, if said goodness ratio is less than a threshold value, said step of quality testing all of said repairable chips being omitted if said goodness ratio is greater than or equal to said threshold value; and (f) quality marking each said defective unrepairable chip and each of said unsuccessfully repaired repairable chips as determined by said quality testing step.
Claim 3
Dependent Claim
33 words
A wafer testing process as in claim 1, wherein said passivation film is composed of any one selected from the group consisting of a PSG film, a nitride film and a combination thereof.
Claim 4
Dependent Claim
50 words
A wafer testing process as in claim 1, wherein step a is carried out by sufficiently over-etching an intermediate insulation film interposed between said passivation film and said program element to make the thickness thereof less than 8,000 Å, for minimizing cutting-off failure of said program elements by said laser-beam.
Claim 5
Dependent Claim
28 words
A wafer testing process as in claim 1, wherein step b is carried out at an operational temperature of said semiconductor device, thereby optimizing the pre-laser test temperature.
Claim 6
Dependent Claim
40 words
A wafer testing process as in claim 1, wherein step d is carried out by performing said final quality test first, and subsequently performing said final quality marking on faulty chips in accordance with results from said final quality test.
Claim 7
Dependent Claim
29 words
The wafer testing process as in claim 1, wherein said quality testing step includes testing each chip for a test condition which exhibits a plurality of potential fault factors.
Claim 8
Dependent Claim
27 words
A wafer testing process as in claim 1, wherein said step a is carried out by opening an alignment mark portion for laser-repairing while simultaneously performing pad-opening.
Claim 9
Dependent Claim
17 words
A testing process as claimed in claim 1, wherein said threshold value in step (e) is 95%.
Claim 10
Dependent Claim
178 words
A wafer testing process comprising the steps of: (a) forming a first protective film over a semiconductor wafer having a plurality of semiconductor chips formed thereon, each said chip having at least one pad for electrical connection and at least one program element; (b) forming a second protective film on said first protective film, said second protective film being a final protective film for said semiconductor wafer; (c) removing a portion of said first and second protective films by a single photolithography step to expose said at least one pad and said at least one program element on each said chip on said wafer; (d) electrically testing every chip on said wafer through said exposed pads to obtain repairing information, including identification of defective but repairable chips and defective and unrepairable chips; (e) repairing said defective but repairable chips on said wafer according to the repairing information obtained in step (d) by cutting said program elements with a laser beam; and (f) quality marking defective chips on said wafer according to the repairing information obtained in step (d).
Claim 11
Dependent Claim
178 words
A wafer testing process comprising the steps of: (a) forming a first protective film over a semiconductor wafer having a plurality of semiconductor chips formed thereon, each said chip having at least one pad for electrical connection and at least one program element; (b) forming a second protective film on said first protective film, said second protective film being a final protective film for said semiconductor wafer; (c) removing a portion of said first and second protective films by a single photolithography step to expose said at least one pad and said at least one program element on each said chip on said wafer; (d) electrically testing every chip on said wafer through said exposed pads to obtain repairing information, including identification of defective but repairable chips and defective and unrepairable chips; (e) repairing said defective but repairable chips on said wafer according to the repairing information obtained in step (d) by cutting said program elements with a laser beam; and (f) quality marking defective chips on said wafer according to the repairing information obtained in step (d).
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1997-07-04 | 1998-01-03 | 1998-07-05 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-07-04 | 2002-01-03 | 2002-07-05 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-07-04 | 2006-01-03 | 2006-07-05 | $7700.00 | Window Closed / Lapsed |