High performance integrated circuit chip package

Claim 2

An integrated circuit chip package comprising: a support substrate having conductors extending from one face to the opposite face thereof, and a multilayer wiring substrate on said opposite face; a plurality of integrated circuit chips, each having a front face and a back face; means for rigidly mounting the front faces of said integrated circuit chips on said multilayer wiring substrate, opposite said support substrate and for electrically connecting the front faces of said integrated circuit chips to said multilayer wiring substrate, such that said integrated circuit chips are electrically connected to one another and to said conductors; a heat sink having microchannels formed therein, said microchannels being adapted for transporting cooling fluid therein, said heat sink being rigidly mounted on said support substrate such that a face of said heat sink is disposed adjacent, and a predetermined fixed distance from, the back face of said integrated circuit chips mounted on said multilayer wiring substrate; and a plurality of thermally conductive cushion layers, a respective one of which extends from said face of said heat sink to said back face of a respective one of said integrated circuit chips, for conducting heat from said integrated circuit chips to said heat sink and for absorbing dimensional variations between the back faces of said integrated circuit chips and said heat sink face during thermal cycling, which results from rigidly mounting said front faces of said integrated circuit chips on said multilayer wiring substrate, and rigidly mounting said heat sink on said support substrate.

Claim 3

The integrated circuit chip package of claim 1 further comprising input/output connectors, electrically connected to respective conductors on said one face of said support substrate, for providing electrical connection to a next level of packaging.

Claim 4

The integrated circuit chip package of claim 2 wherein said input/output connectors comprise metal pins which are electrically connected to respective conductors.

Claim 5

The integrated circuit chip package of claim 2 wherein said input/output connectors comprise metal pads which are electrically connected to respective conductors.

Claim 6

The integrated circuit chip package of claim 1 wherein said integrated circuit chips are formed of silicon semiconductor material, and wherein said support substrate and said heat sink are formed of materials having a coefficient of thermal expansion which closely matches that of silicon.

Claim 7

The integrated circuit chip package of claim 5 wherein said support substrate and said heat sink are formed of silicon carbide.

Claim 8

The integrated circuit chip package of claim 5 wherein said support, substrate and said heat sink are formed of silicon.

Claim 9

The integrated circuit chip package of claim 5 wherein said support substrate is formed of aluminum nitride or silicon carbide and said heat sink is formed of aluminum nitride or silicon carbide.

Claim 10

The integrated circuit chip package of claim 1 wherein said multilayer wiring substrate comprises a plurality of insulating layers having conductive vias and conductive planes therein.

Claim 11

The integrated circuit chip package of claim 9 wherein said conductive vias comprise a first conductor and a second conductor on the sides thereof.

Claim 12

The integrated circuit chip package of claim 9 wherein said conductive planes comprise a a power plane, a ground plane, an X signal plane and a Y signal plane.

Claim 13

The integrated circuit chip package of claim 1 wherein said rigidly mounting means comprises a plurality of solder bumps for rigidly mounting said integrated circuit chips on said multilayer wiring substrate.

Claim 14

The integrated circuit chip package of claim 1 wherein said integrated circuit chips are about 1 cm square, and said microchannels are 1 mm deep, spaced 1 mm apart, having a width of 5 mm each and are located 1 mm below said face of said heat sink.

Claim 15

The integrated circuit chip package of claim 1 wherein each of said thermally conductive cushion layers is a layer of reflowed solder.

Claim 16

The integrated circuit chip package of claim 14 wherein said reflowed solder is a soft, low melting point solder.

Claim 17

The integrated circuit chip package of claim 14 wherein said solder is indium.

Claim 18

The integrated circuit chip package of claim 16 wherein said indium is about 650 μm thick.

Claim 19

The integrated circuit chip package of claim 14 wherein said solder is an alloy of indium.

Claim 20

The integrated circuit chip package of claim 1 wherein said thermally conductive cushion layers comprise solder preforms and wherein said heat sink includes a plurality of cavities at said one end for holding said preforms.

Claim 21

The integrated circuit chip package of claim 1 wherein said thermally conductive cushion layers are sufficiently thin to efficiently conduct heat from said integrated circuit chips to said heat sink, but sufficiently thick to cushion against dimensional variations and thermal expansions in said package.

Claim 22

The integrated circuit chip package of claim 1 wherein said support substrate comprises a pin support substrate and a wiring support substrate.

Claim 23

The integrated circuit chip package of claim 1 wherein said support substrate is a monolithic piece of insulating material having said plurality of conductors extending from said one face to said opposite face thereof.

Claim 24

An integrated circuit chip package comprising: a plurality of integrated circuit chips, each having a front face and a back face; a first ceramic block having conductors extending therethrough from one face to the opposite face thereof, said first ceramic block being free of power, ground and signal panes therein; input/output connectors, electrically connected to respective conductors on said one face of said first ceramic block, for providing electrical connection to a next level of packaging; a multilayer wiring substrate on said opposite face of said first ceramic block, said multilayer wiring substrate comprising a plurality of insulating layers having conductive vias and conductive power, ground and signal planes therein, for providing power, ground and signal connections from said conductors; controller collapse chip connections for rigidly mounting the front face of said integrated circuit chips on said multilayer wiring substrate; a second ceramic block having microchannels formed therein at one face thereof for transporting cooling fluid therein, said second ceramic block being rigidly mounted on said first ceramic block such that said one face is disposed adjacent, and a predetermined fixed distance from, said back faces of said integrated circuit chips mounted on said multilayer wiring substrate; and a plurality of layers of indium or an alloy thereof, a respective one of which extends between a respective one of said back faces of said integrated circuit chips and said one face of said second block of ceramic, each layer of indium or an alloy thereof being sufficiently thin to efficiently conduct heat from said chips to said second block but sufficiently thick to absorb dimensional variations and thermal expansions in said package which result from the rigid mounting of said controlled collapse chip connections between said integrated circuit chips and said multilayer wiring substrate and from rigidly mounting said second ceramic block on said first ceramic block.

Claim 25

An integrated circuit chip package comprising: a plurality of integrated circuit chips, each having a front face and a back face; a first ceramic block having conductors extending therethrough from one face to the opposite face thereof, said first ceramic block being free of power, ground and signal panes therein; input/output connectors, electrically connected to respective conductors on said one face of said first ceramic block, for providing electrical connection to a next level of packaging; a multilayer wiring substrate on said opposite face of said first ceramic block, said multilayer wiring substrate comprising a plurality of insulating layers having conductive vias and conductive power, ground and signal planes therein, for providing power, ground and signal connections from said conductors; controller collapse chip connections for rigidly mounting the front face of said integrated circuit chips on said multilayer wiring substrate; a second ceramic block having microchannels formed therein at one face thereof for transporting cooling fluid therein, said second ceramic block being rigidly mounted on said first ceramic block such that said one face is disposed adjacent, and a predetermined fixed distance from, said back faces of said integrated circuit chips mounted on said multilayer wiring substrate; and a plurality of layers of indium or an alloy thereof, a respective one of which extends between a respective one of said back faces of said integrated circuit chips and said one face of said second block of ceramic, each layer of indium or an alloy thereof being sufficiently thin to efficiently conduct heat from said chips to said second block but sufficiently thick to absorb dimensional variations and thermal expansions in said package which result from the rigid mounting of said controlled collapse chip connections between said integrated circuit chips and said multilayer wiring substrate and from rigidly mounting said second ceramic block on said first ceramic block.

Claim 26

The integrated circuit chip package of claim 23 wherein said input/output connectors are metal pins which are electrically connected to respective conductors.

Claim 27

The integrated circuit chip package of claim 23 wherein said first and second ceramic blocks are silicon carbide.

Claim 28

The integrated circuit chip package of claim 23 wherein said first ceramic block is aluminum nitride and said second ceramic block is silicon carbide.

Claim 29

The integrated circuit chip package of claim 23 wherein said conductive vias comprise a first conductor and a second conductor on the sides thereof.

Claim 30

The integrated circuit chip package of claim 23 wherein said integrated circuits are about 1 cm square, and said microchannels are 1 mm deep, spaced 1 mm apart, having a width of 5 mm each, and are located 1 mm below said one face of said second ceramic block.

Claim 31

The integrated circuit chip package of claim 23 wherein said indium is about 650 μm thick.