Low voltage CMOS bandgap with new trimming and curvature correction methods

Claim 2

A low voltage bandgap circuit, coupled between a power supply terminal and ground, comprising: a first plurality of PNP transistors having grounded collector terminals, with a base terminal of each of said first plurality of PNP transistors coupled to an emitter terminal of a next one of said first plurality of PNP transistors; a second plurality of PNP transistors having grounded collector terminals, with a base terminal of each of said second plurality of PNP transistors coupled to an emitter terminal of a next one of said second plurality of PNP transistors; a first plurality of load devices, each coupling an emitter terminal of a corresponding one of said first plurality of PNP transistors to the power supply; a second plurality of load devices, each coupling an emitter terminal of a corresponding one of said second plurality of PNP transistors to the power supply; a CMOS amplifier having NMOS input transistors, with a first input coupled to an emitter terminal of a first one of said first plurality of PNP transistors, a second input coupled to an emitter terminal of a first one of said second plurality of PNP transistors, and an output coupled to the bandgap circuit output; a first resistor having a first terminal coupled to said amplifier output and a second terminal coupled to a base terminal of a last one of said second plurality of PNP transistors; a second resistor having a first terminal coupled to said first resistor second terminal and a second terminal coupled to a base terminal of a last one of said first plurality of PNP transistors; and a diode connected PNP transistor having an emitter terminal coupled to said second resistor second terminal, and a base and collector terminal coupled to ground.

Claim 3

The low voltage bandgap circuit of claim 1, wherein a size of each one of said second plurality of PNP transistors is a factor of N larger than a size of each corresponding one of said first plurality of PNP transistors.

Claim 4

The low voltage bandgap circuit of claim 2, further comprising a transistor trimming circuit having a plurality of control inputs, said transistor trimming circuit further comprising: at least one trim down PNP transistor having grounded collector terminal, with emitter terminal coupled to said amplifier first input; at least one trip up PNP transistor having grounded collector terminal, with emitter terminal coupled to said amplifier second input; at least one trim down switch, coupling a base terminal of a corresponding one of said at least one trim down PNP transistor to a base terminal of said first one of said first plurality of PNP transistors; at least one trim up switch, coupling a base terminal of a corresponding one of said at least one trip up PNP transistor to a base terminal of said first one of said second plurality of PNP transistors; and a switch control circuit having a plurality of inputs coupled to said plurality of transistor trimming circuit inputs, and a plurality of outputs each coupled to a control terminal of each one of said at least one trim down and at least one trim up switches, respectively.

Claim 5

The low voltage bandgap circuit of claim 3, wherein a size of each one of said plurality of trim up PNP transistors is progressively binary weighted.

Claim 6

A low voltage bandgap circuit, coupled between a power supply terminal and ground, comprising: a first plurality of PNP transistors having grounded collector terminals, with a base terminal of each of said first plurality of PNP transistors coupled to an emitter terminal of a next one of said first plurality of PNP transistors; a second plurality of PNP transistors having grounded collector terminals, with a base terminal of each of said second plurality of PNP transistors coupled to an emitter terminal of a next one of said second plurality of PNP transistors; a first plurality of load devices, each coupling an emitter terminal of a corresponding one of said first plurality of PNP transistors to the power supply; a second plurality of load devices, each coupling an emitter terminal of a corresponding one of said second plurality of PNP transistors to the power supply; an amplifier having a first input coupled to an emitter terminal of a first one of said first plurality of PNP transistors, a second input coupled to an emitter terminal of a first one of said second plurality of PNP transistors, and an output coupled to the bandgap circuit output; a first resistor having a first terminal coupled to said amplifier output and a second terminal coupled to a base terminal of a last one of said second plurality of PNP transistors; a second resistor having a first terminal coupled to said first resistor second terminal and a second terminal coupled to a base terminal of a last one of said first plurality of PNP transistors; a third resistor having a first terminal coupled to said second resistor second terminal; and a diode connected PNP transistor having an emitter terminal coupled to a second terminal of said third resistor, and a base and collector terminal coupled to ground.

Claim 7

A low voltage bandgap circuit, coupled between a power supply terminal and ground, comprising: a first plurality of PNP transistors having grounded collector terminals, with a base terminal of each of said first plurality of PNP transistors coupled to an emitter terminal of a next one of said first plurality of PNP transistors; a second plurality of PNP transistors having grounded collector terminals, with a base terminal of each of said second plurality of PNP transistors coupled to an emitter terminal of a next one of said second plurality of PNP transistors; a first plurality of load devices, each coupling an emitter terminal of a corresponding one of said first plurality of PNP transistors to the power supply; a second plurality of load devices, each coupling an emitter terminal of a corresponding one of said second plurality of PNP transistors to the power supply; an amplifier having a first input coupled to an emitter terminal of a first one of said first plurality of PNP transistors, a second input coupled to an emitter terminal of a first one of said second plurality of PNP transistors, and an output coupled to the bandgap circuit output; a first resistor having a first terminal coupled to said amplifier output and a second terminal coupled to a base terminal of a last one of said second plurality of PNP transistors; a second resistor having a first terminal coupled to said first resistor second terminal and a second terminal coupled to a base terminal of a last one of said first plurality of PNP transistors; a third resistor having a first terminal coupled to said second resistor second terminal; and a diode connected PNP transistor having an emitter terminal coupled to a second terminal of said third resistor, and a base and collector terminal coupled to ground.

Claim 8

A low voltage bandgap circuit, coupled between a power supply terminal and ground, comprising: a first plurality of PNP transistors having grounded collector terminals, with a base terminal of each of said first plurality of PNP transistors coupled to an emitter terminal of a next one of said first plurality of PNP transistors; a second plurality of PNP transistors having grounded collector terminals, with a base terminal of each of said second plurality of PNP transistors coupled to an emitter terminal of a next one of said second plurality of PNP transistors; a first plurality of load devices, each coupling an emitter terminal of a corresponding one of said first plurality of PNP transistors to the power supply; a second plurality of load devices, each coupling an emitter terminal of a corresponding one of said second plurality of PNP transistors to the power supply; a CMOS amplifier having NMOS input transistors, with a first input coupled to an emitter terminal of a fist one of said first plurality of PNP transistors, a second input coupled to an emitter terminal of a first one of said second plurality of PNP transistors, and an output coupled to the bandgap circuit output; a first resistor having a first terminal coupled to said amplifier output and a second terminal coupled to a base terminal of a last one of said second plurality of PNP transistors; a second resistor having a first terminal coupled to said first resistor second terminal and a second terminal coupled to a base terminal of a last one of said first plurality of PNP transistors; a third resistor having a first terminal coupled to said second resistor second terminal; a diode connected PNP transistor having an emitter terminal coupled to a second terminal of said third resistor, and a base and collector terminal coupled to ground; at least one trim down PNP transistor having grounded collector terminal, with emitter terminal coupled to said amplifier first input; at least one trim up PNP transistor having grounded collector terminal, with emitter terminal coupled to said amplifier second input; at least one trim down switch, coupling a base terminal of a corresponding one of said at least one trim down PNP transistor to a base terminal of said first one of said first plurality of PNP transistors; at least one trim up switch, coupling a base terminal of a corresponding one of said at least one trim up PNP transistor to a base terminal of said first one of said second plurality of PNP transistors; and a switch control circuit having a plurality of inputs coupled to said plurality of transistor trimming circuit inputs, and a plurality of outputs each coupled to a control terminal of each one of said at least one trim down and at least one trim up switches, respectively.

Claim 9

A low voltage bandgap circuit, coupled between a power supply terminal and ground, comprising: a first plurality of PNP transistors having grounded collector terminals, with a base terminal of each of said first plurality of PNP transistors coupled to an emitter terminal of a next one of said first plurality of PNP transistors; a second plurality of PNP transistors having grounded collector terminals, with a base terminal of each of said second plurality of PNP transistors coupled to an emitter terminal of a next one of said second plurality of PNP transistors; a first plurality of load devices, each coupling an emitter terminal of a corresponding one of said first plurality of PNP transistors to the power supply; a second plurality of load devices, each coupling an emitter terminal of a corresponding one of said second plurality of PNP transistors to the power supply; a CMOS amplifier having NMOS input transistors, with a first input coupled to an emitter terminal of a fist one of said first plurality of PNP transistors, a second input coupled to an emitter terminal of a first one of said second plurality of PNP transistors, and an output coupled to the bandgap circuit output; a first resistor having a first terminal coupled to said amplifier output and a second terminal coupled to a base terminal of a last one of said second plurality of PNP transistors; a second resistor having a first terminal coupled to said first resistor second terminal and a second terminal coupled to a base terminal of a last one of said first plurality of PNP transistors; a third resistor having a first terminal coupled to said second resistor second terminal; a diode connected PNP transistor having an emitter terminal coupled to a second terminal of said third resistor, and a base and collector terminal coupled to ground; at least one trim down PNP transistor having grounded collector terminal, with emitter terminal coupled to said amplifier first input; at least one trim up PNP transistor having grounded collector terminal, with emitter terminal coupled to said amplifier second input; at least one trim down switch, coupling a base terminal of a corresponding one of said at least one trim down PNP transistor to a base terminal of said first one of said first plurality of PNP transistors; at least one trim up switch, coupling a base terminal of a corresponding one of said at least one trim up PNP transistor to a base terminal of said first one of said second plurality of PNP transistors; and a switch control circuit having a plurality of inputs coupled to said plurality of transistor trimming circuit inputs, and a plurality of outputs each coupled to a control terminal of each one of said at least one trim down and at least one trim up switches, respectively.

Claim 10

The low voltage bandgap circuit of claim 2, wherein said first and second plurality of load devices are current source loads, with sizes which cause a magnitude of current in each one of said first plurality of current source loads a factor of N times larger than a magnitude of current in each one of said second plurality of current source loads.

Claim 11

The low voltage bandgap circuit of claim 7, further comprising a current trimming circuit having a plurality of inputs, said current trimming circuit further comprising: at least one trim down current source load coupled in parallel to one of said second plurality of current source loads, and having a control terminal coupled to a corresponding one of said plurality of current trimming circuit inputs; and at least one trim up current source load coupled in parallel to one of said first plurality of current source loads, and having a control terminal coupled to a corresponding one of said plurality of current trimming circuit inputs.

Claim 12

The low voltage bandgap circuit of claim 1, wherein said first and second resistors are of a type having a negative temperature coefficient.

Claim 13

The low voltage bandgap circuit of claim 5, wherein said first, second, and third resistors are of a type having a negative temperature coefficient.

Claim 14

The low voltage bandgap circuit of claim 6, wherein said first, second, and third resistors are of a type having a negative temperature coefficient.

Claim 15

In a bandgap reference circuit that generates a delta V be term by ratioing a size of a first bipolar transistor coupled to a first input of an amplifier, to a second bipolar transistor coupled to a second input of the amplifier, a new trimming circuit comprising: at least one trim down bipolar transistor coupled in parallel to the first bipolar transistor; and at least one trim up bipolar transistor coupled in parallel to the second bipolar transistor, wherein, the size ratioing between the first and the second bipolar transistor is changed by activating a combination of said at least one trim down or trim up bipolar transistors to trim the bandgap reference.

Claim 16

In a bandgap reference circuit that generates a delta V be term by ratioing a size of a first bipolar transistor coupled to a first input of an amplifier, to a second bipolar transistor coupled to a second input of the amplifier, a new trimming circuit comprising: at least one trim down bipolar transistor coupled in parallel to the first bipolar transistor; and at least one trim up bipolar transistor coupled in parallel to the second bipolar transistor, wherein, the size ratioing between the first and the second bipolar transistor is changed by activating a combination of said at least one trim down or trim up bipolar transistors to trim the bandgap reference.

Claim 17

The trimming circuit of claim 12, wherein at least one of said one trim down and trim up bipolar transistors is a plurality of bipolar transistors having transistor sizes that are progressively binary weighted.

Claim 18

The trimming circuit of claim 12, wherein said at least one trim down and trim up bipolar transistors couple in parallel to said first and said second bipolar transistors through respective switches.

Claim 19

In a bandgap reference circuit that generates a delta V be term by ratioing a magnitude of current in a first current source load for a first bipolar transistor coupled to a first input of an amplifier, to a magnitude of current in a second current source load for a second bipolar transistor coupled to a second input of the amplifier, a new trimming circuit comprising: at least one trim down current source load coupled in parallel to the first current source load; and at least one trim up current source load coupled in parallel to the second current source load, wherein, the ratio of the magnitude of current in the first current source load to the magnitude of current in the second current source load is changed by turning on a combination of said at least one trim down and trim up current source loads to trim the bandgap reference circuit.

Claim 20

In a bandgap reference circuit that generates a delta V be term by ratioing a magnitude of current in a first current source load for a first bipolar transistor coupled to a first input of an amplifier, to a magnitude of current in a second current source load for a second bipolar transistor coupled to a second input of the amplifier, a new trimming circuit comprising: at least one trim down current source load coupled in parallel to the first current source load; and at least one trim up current source load coupled in parallel to the second current source load, wherein, the ratio of the magnitude of current in the first current source load to the magnitude of current in the second current source load is changed by turning on a combination of said at least one trim down and trim up current source loads to trim the bandgap reference circuit.

Claim 21

The trimming circuit of claim 15, wherein at least one of said at least one trim down and trim up current source loads is a plurality of current source loads having load sizes that are progressively binary weighted.

Claim 22

The trimming circuit of claim 15, wherein said at least one trim down and trim up current source loads coupled in parallel to said first and second current source load through respective switches.

Claim 23

In a bandgap reference circuit having a device generating a Vbe term, an improved curvature correction means for inducing a current with increased positive temperature coefficient through said device.

Claim 24

In a bandgap reference circuit having a device generating a Vbe term, an improved curvature correction means for inducing a current with increased positive temperature coefficient through said device.

Claim 25

The curvature correction means of claim 18 wherein the bandgap reference circuit uses a ratio of a first resistor to a second resistor to generate a constant factor multiplying a delta V be term, and wherein said first and second resistors are of a type having a negative temperature coefficient to induce said current with a positive temperature coefficient through said device.

Claim 26

A low voltage bandgap circuit, coupled between a power supply terminal and ground, comprising: a first PNP transistor having a grounded collector terminal, a base terminal, and an emitter terminal; a second PNP transistor having a grounded collector terminal, a base terminal, and an emitter terminal; a first load device coupling said emitter terminal of said first PNP transistor to the power supply; a second load device coupling said emitter terminal of said second PNP transistor to the power supply; a second load device coupling said emitter terminal of said second PNP transistor to the power supply; a CMOS amplifier having NMOS input transistors, with a first input coupled to said emitter terminal of said first PNP transistor, a second input coupled to said emitter terminal of said second PNP transistor, and an output coupled to the bandgap circuit output; a first resistor having a first terminal coupled to said amplifier output and a second terminal coupled to said base terminal of said second PNP transistor; a second resistor having a first terminal coupled to said first resistor second terminal and a second terminal coupled to said base terminal of said first PNP transistor; and a diode connected PNP transistor having an emitter terminal coupled to said second resistor second terminal, and a base and collector terminal coupled to ground.

Claim 27

A low voltage bandgap circuit, coupled between a power supply terminal and ground, comprising: a first PNP transistor having a grounded collector terminal, a base terminal, and an emitter terminal; a second PNP transistor having a grounded collector terminal, a base terminal, and an emitter terminal; a first load device coupling said emitter terminal of said first PNP transistor to the power supply; a second load device coupling said emitter terminal of said second PNP transistor to the power supply; a second load device coupling said emitter terminal of said second PNP transistor to the power supply; a CMOS amplifier having NMOS input transistors, with a first input coupled to said emitter terminal of said first PNP transistor, a second input coupled to said emitter terminal of said second PNP transistor, and an output coupled to the bandgap circuit output; a first resistor having a first terminal coupled to said amplifier output and a second terminal coupled to said base terminal of said second PNP transistor; a second resistor having a first terminal coupled to said first resistor second terminal and a second terminal coupled to said base terminal of said first PNP transistor; and a diode connected PNP transistor having an emitter terminal coupled to said second resistor second terminal, and a base and collector terminal coupled to ground.

Claim 28

The low voltage bandgap circuit of claim 20, wherein a size of said second PNP transistor is a factor of N larger than a size of said first plurality of PNP transistor.