Trim correction circuit with temperature coefficient compensation

Claim 2

An operational amplifier bias system that provides input offset voltage trim current to an operational amplifier with minimum offset thermal drift, the bias system comprising: a bias generator that provides bias generator current to the operational amplifier; and correction means responsive to the bias generator current for providing an input offset trim current to the operational amplifier that compensates for offset drift error of the input offset voltage of the operational amplifier with change in temperature, the correction means including a resistive element, an input current mirror responsive to the bias generator current for providing a reference current to the resistive element to provide a temperature coefficient conversion current having a predetermined temperature coefficient, a second current mirror responsive to the bias generator current for providing a temperature coefficient correction current, current summing means for summing the temperature coefficient conversion current and the temperature coefficient conversion current to provide an output current having a predetermined temperature coefficient, and a trim bit network responsive to the output current for providing the input offset voltage trim current.

Claim 5

An op amp bias system as in claim 1 wherein the resistive element comprises a linear resistive element.

Claim 6

An op amp bias system as in claim 1 and further comprising feedback means for linearizing the resistive element.

Claim 7

An op amp bias system as in claim 1 wherein the resistive element comprises an active resistor.

Claim 8

An op amp bias system as in claim 5 wherein the active resistor comprises a MOSFET device biased for operation in the triode region.

Claim 9

An operational amplifier bias circuit for providing temperature compensated trim current to a CMOS operational amplifier to compensate for input offset voltage, the circuit comprising: (a) a first current mirror that includes a first diode-connected N-channel mirror transistor and a second N-channel mirror transistor, the gate of the first mirror transistor being connected to the gate of the second mirror transistor, the body of the second mirror transistor being connected to the body and to the source of the first mirror transistor; (b) a diode-connected N-channel threshold voltage reference transistor operable in the sub-threshold range and having its drain connected to the source of the first mirror transistor and its source connected to a negative supply; (c) an N-channel resistive transistor operable in the triode mode, and having its drain connected to the source of the second mirror transistor and its source connected to the negative supply; (d) a second current mirror that includes a first diode-connected P-channel mirror transistor having its source connected to a positive supply and its drain connected to the drain of the second N-channel mirror transistor, and a second P-channel mirror transistor having its source connected to the positive power supply, its gate connected to the gate of the first P-channel transistor and its drain connected to provide compensation current to a load of the operational amplifier's input differential pair; (e) an N-channel temperature coefficient correction transistor having its drain connected to the drain of the first P-channel mirror transistor, its source connected to the negative supply and its gate connected to the gate of the threshold voltage reference transistor; and (f) a curvature correction network that includes a P-channel curvature correction transistor having its source connected to the positive supply and its gate connected to the commonly-connected gates of the first and second P-channel mirror transistors and a N-channel curvature correction transistor having its source connected to the negative supply, its drain connected to the drain of the P-channel curvature correction transistor, and its gate connected both to its drain and to the gate of the N-channel resistive transistor.

Claim 10

An operational amplifier bias circuit for providing temperature compensated trim current to a CMOS operational amplifier to compensate for input offset voltage, the circuit comprising: (a) a first current mirror that includes a first diode-connected N-channel mirror transistor and a second N-channel mirror transistor, the gate of the first mirror transistor being connected to the gate of the second mirror transistor, the body of the second mirror transistor being connected to the body and to the source of the first mirror transistor; (b) a diode-connected N-channel threshold voltage reference transistor operable in the sub-threshold range and having its drain connected to the source of the first mirror transistor and its source connected to a negative supply; (c) an N-channel resistive transistor operable in the triode mode, and having its drain connected to the source of the second mirror transistor and its source connected to the negative supply; (d) a second current mirror that includes a first diode-connected P-channel mirror transistor having its source connected to a positive supply and its drain connected to the drain of the second N-channel mirror transistor, and a second P-channel mirror transistor having its source connected to the positive power supply, its gate connected to the gate of the first P-channel transistor and its drain connected to provide compensation current to a load of the operational amplifier's input differential pair; (e) an N-channel temperature coefficient correction transistor having its drain connected to the drain of the first P-channel mirror transistor, its source connected to the negative supply and its gate connected to the gate of the threshold voltage reference transistor; and (f) a curvature correction network that includes a P-channel curvature correction transistor having its source connected to the positive supply and its gate connected to the commonly-connected gates of the first and second P-channel mirror transistors and a N-channel curvature correction transistor having its source connected to the negative supply, its drain connected to the drain of the P-channel curvature correction transistor, and its gate connected both to its drain and to the gate of the N-channel resistive transistor.