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US5324992A
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Self-timing integrated circuits having low clock signal during inactive periods
Assignee: Carnegie Mellon University
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Filing: 1992-07-01
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Granted: 1994-06-28
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Expires: 2012-07-01
Abstract
Abstract An integrated circuit function unit operating in a data dependent manner in logic operations of variable lengths of time is provided with a clock signal having a pulse width determined by the active period of the function unit. In one embodiment a current sensor monitors power supply current to the integrated circuit, and when the current exceeds a threshold level the integrated circuit is in an active period. Clock means for generating a clock signal for the function unit responds to the sensed current in controlling the clock period.
Inventors
- 👤 Wojciech Maly
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 16:24
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/0008; H03K19/0016; H03K17/00; H03K17/30; H03K17/302
Claims Analysis
Total Claims: 15
Claim 1
Independent Claim
97 words
A self-timing integrated circuit comprising: a clocked function unit responsive to a clock signal for operating on variable numbers in logic operations of variable lengths of time, said function unit having an active period during a logic operation and an inactive period following a logic operation, sensing means for monitoring said function unit to identify active periods, clock means for generating a clock signal for said function unit, said clock signal having variable width pulses, and means coupling said sensing means to said clock means for controlling said variable width pulses in response to identified active periods.
Claim 2
Dependent Claim
97 words
A self-timing integrated circuit comprising: a clocked function unit responsive to a clock signal for operating on variable numbers in logic operations of variable lengths of time, said function unit having an active period during a logic operation and an inactive period following a logic operation, sensing means for monitoring said function unit to identify active periods, clock means for generating a clock signal for said function unit, said clock signal having variable width pulses, and means coupling said sensing means to said clock means for controlling said variable width pulses in response to identified active periods.
Claim 3
Dependent Claim
33 words
The self-timing integrated circuit as defined by claim 1 wherein said sensing means comprises voltage supply current sensing means, an active period being identified when the voltage supply current exceeds a threshold value.
Claim 4
Dependent Claim
37 words
The self-timing integrated circuit defined by claim 2 wherein said clock means includes bistable circuit means having two output voltage levels corresponding to voltage supply currents exceeding said threshold level and not exceeding said threshold level, respectively.
Claim 5
Dependent Claim
38 words
The self-timing integrated circuit as defined by claim 1 wherein said clock means includes bistable circuit means having two output voltage levels corresponding to voltage supply currents exceeding a threshold level and not exceeding said threshold level, respectively.
Claim 6
Dependent Claim
16 words
The self-timing integrated circuit as defined by claim 1 wherein said integrated circuit comprises CMOS circuitry.
Claim 7
Dependent Claim
78 words
Apparatus for controlling the clock period for clock pulses applied to a clocked integrated circuit powered by a voltage supply comprising: sensing means for sensing current from said voltage supply to said integrated circuit and determining when said current exceeds a threshold level indicative of said integrated circuit being in an active state, and clocking means responsive to said sensing means for controlling pulse width of said clock pulses whereby positive pulses are provided during an active state.
Claim 8
Dependent Claim
78 words
Apparatus for controlling the clock period for clock pulses applied to a clocked integrated circuit powered by a voltage supply comprising: sensing means for sensing current from said voltage supply to said integrated circuit and determining when said current exceeds a threshold level indicative of said integrated circuit being in an active state, and clocking means responsive to said sensing means for controlling pulse width of said clock pulses whereby positive pulses are provided during an active state.
Claim 9
Dependent Claim
35 words
Apparatus as defined by claim 6 wherein said clock means includes bistable circuit means having two output voltage levels corresponding to voltage supply currents exceeding said threshold level and not exceeding said threshold level, respectively.
Claim 10
Independent Claim
62 words
A method of clocking an integrated circuit having active periods and inactive periods and which operates in response to positive pulses of a clock signal comprising the steps of: (a) monitoring said integrated circuit to identify active periods, (b) providing positive pulses to said integrated circuit during said active periods, and (c) removing positive pulses from said integrated circuit during inactive periods.
Claim 11
Independent Claim
62 words
A method of clocking an integrated circuit having active periods and inactive periods and which operates in response to positive pulses of a clock signal comprising the steps of: (a) monitoring said integrated circuit to identify active periods, (b) providing positive pulses to said integrated circuit during said active periods, and (c) removing positive pulses from said integrated circuit during inactive periods.
Claim 12
Dependent Claim
31 words
The method as defined by claim 8 wherein step (a) includes sensing power supply current to said integrated circuit, supply current above a threshold level being indicative of an active period.
Claim 13
Independent Claim
65 words
A method of providing timing to an integrated circuit function unit which logically operates on variable length numbers during active periods of variable lengths of time comprising the steps of: (a) generating a clock signal having variable clock pulses for said integrated circuit, (b) monitoring said integrated circuit to identify active periods, and (c) controlling said variable clock pulses in response to identified active periods.
Claim 14
Independent Claim
65 words
A method of providing timing to an integrated circuit function unit which logically operates on variable length numbers during active periods of variable lengths of time comprising the steps of: (a) generating a clock signal having variable clock pulses for said integrated circuit, (b) monitoring said integrated circuit to identify active periods, and (c) controlling said variable clock pulses in response to identified active periods.
Claim 15
Dependent Claim
32 words
The method as defined by claim 10 wherein step (b) includes sensing power supply current to said integrated circuit whereby supply current above a threshold level is indicative of an active period.
References Cited (Backward Citations)
US4387449A
Cited
US4851987A
Cited
US4697097A
Cited
US4716463A
Cited
US5025344A
Cited
US4999516A
Cited
US5128558A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1997-06-27 | 1997-12-27 | 1998-06-28 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-06-27 | 2001-12-27 | 2002-06-28 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-06-27 | 2005-12-27 | 2006-06-28 | $7700.00 | Window Closed / Lapsed |