Method of making an integrated circuit capable of low-noise and high-power microwave operation

Claim 1

A method of fabricating an integrated circuit for providing low-noise and high-power microwave operation comprising: a) forming a donor layer above a substrate; b) forming a first wide bandgap buffer layer above said planar donor layer; c) forming an undoped first channel layer above said first wide bandgap layer; d) forming a second channel layer above said first channel layer; e) forming a second wide bandgap layer above said second channel layer; f) forming a cap layer above said second wide bandgap layer; g) forming a first transistor configuration by forming a first recess that extends through said cap layer, said second wide bandgap layer, and into said second channel layer in a first pattern; h) forming a second transistor configuration by forming a second recess that extends through said cap layer and slightly into said second wide bandgap layer; i) forming a third recess inside of said first recess that extends through said second channel layer; j) forming a fourth recess inside of said second recess that extends further into said second wide bandgap layer than said second recess; k) forming a first gate contact in said third recess; l) forming a second gate contact in said fourth recess; m) forming a first drain contact on said cap layer on one side of said first recess and a first source contact on an opposite side of said first recess; and n) forming a second drain contact on said cap layer on one side of said second recess and a second source contact on an opposite side of said second recess, wherein said contacts are alloyed and driven through said cap layer, said second wide bandgap layer, said second channel layer and said first wide bandgap layer to make contact with first channel layer and said second channel layer.

Claim 2

A method of fabricating an integrated circuit for providing low-noise and high-power microwave operation comprising: a) forming a donor layer above a substrate; b) forming a first wide bandgap buffer layer above said planar donor layer; c) forming an undoped first channel layer above said first wide bandgap layer; d) forming a second channel layer above said first channel layer; e) forming a second wide bandgap layer above said second channel layer; f) forming a cap layer above said second wide bandgap layer; g) forming a first transistor configuration by forming a first recess that extends through said cap layer, said second wide bandgap layer, and into said second channel layer in a first pattern; h) forming a second transistor configuration by forming a second recess that extends through said cap layer and slightly into said second wide bandgap layer; i) forming a third recess inside of said first recess that extends through said second channel layer; j) forming a fourth recess inside of said second recess that extends further into said second wide bandgap layer than said second recess; k) forming a first gate contact in said third recess; l) forming a second gate contact in said fourth recess; m) forming a first drain contact on said cap layer on one side of said first recess and a first source contact on an opposite side of said first recess; and n) forming a second drain contact on said cap layer on one side of said second recess and a second source contact on an opposite side of said second recess, wherein said contacts are alloyed and driven through said cap layer, said second wide bandgap layer, said second channel layer and said first wide bandgap layer to make contact with first channel layer and said second channel layer.