Patent US5322816A successfully refreshed from Google Patents.
US5322816A
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Method for forming deep conductive feedthroughs
Assignee: Raytheon Co
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Filing: 1993-01-19
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Granted: 1994-06-21
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Expires: 2013-01-19
Abstract
Abstract An interconnect layer (40) for interposing between two active circuit layers of a multi-chip module (50). The interconnect layer includes a layer of silicon (14) having first surface and second surfaces. A first layer of dielectric material (16) is disposed over the first surface and a second layer of dielectric material (12) disposed over the second surface. The interconnect layer includes at least one electrically conductive feedthrough (42) that is formed within an opening made through the layer of silicon. The opening has sidewalls (22) that are coated with a dielectric material (24) and an electrically conductive material for providing a topside contact (26). A second contact (28) is formed from the backside of the silicon layer after removing the substrate (10). In accordance with the invention, the sidewalls have a slope associated therewith such that an area of the opening is larger at the first surface of the silicon layer than at the second surface of the silicon layer, thereby improving the contact metal step coverage. The silicon layer is comprised of <100> silicon and has a thickness in the range of approximately 10 micrometers to approximately 50 micrometers. The opening is etched through the <100> silicon layer with KOH to provide an inwardly sloping sidewall profile having an angle that is approximately equal to 54.7 degrees.
Inventors
- 👤 Jerald F. Pinter
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 10:23
CPC Classifications
H; H10; H10P; H10P90/00; H10P90/19; H10P90/1904; H10P90/1906; H10P90/1914; H10W; H10W10/00; H10W10/10; H10W10/181; H10W20/00; H10W20/01; H10W20/021; H10W20/023; H10W20/0245; Y; Y10; Y10S; Y10S148/00; Y10S148/135; Y10S148/164; Y10S438/00; Y10S438/928; Y10S438/973
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
274 words
A method of forming an electrically conductive feedthrough within a semiconductor layer, comprising the steps of: providing a multilayered structure that includes a substrate, a layer of dielectric material having a first surface that overlies a surface of the substrate and a second surface that is opposite to the first surface, and a semiconductor layer having a first surface that overlies the second surface of the layer of dielectric material and a second surface that is opposite the first surface of the semiconductor layer; forming at least one opening through the semiconductor layer to expose an underlying portion of the second surface of the dielectric layer, the opening having sidewalls that are coated with a dielectric material, the sidewalls having a slope associated therewith such that an area of the opening is larger at the second surface of the semiconductor layer than at the first surface of the semiconductor layer; depositing an electrically conductive material upon the tapered sidewalls and upon the exposed portion of the second surface of the dielectric layer; removing the substrate to expose the first surface of the dielectric layer; forming an opening through the dielectric layer, the opening being formed in registration with the opening through the semiconductor layer and exposing a portion of the electrically conductive material that was deposited upon the portion of the second surface of the dielectric layer; and depositing an electrically conductive material within the opening formed through the dielectric layer such that the electrically conductive material that was deposited within the opening through the semiconductor layer is electrically coupled to the electrically conductive material that is within the opening through the dielectric layer.
Claim 2
Independent Claim
274 words
A method of forming an electrically conductive feedthrough within a semiconductor layer, comprising the steps of: providing a multilayered structure that includes a substrate, a layer of dielectric material having a first surface that overlies a surface of the substrate and a second surface that is opposite to the first surface, and a semiconductor layer having a first surface that overlies the second surface of the layer of dielectric material and a second surface that is opposite the first surface of the semiconductor layer; forming at least one opening through the semiconductor layer to expose an underlying portion of the second surface of the dielectric layer, the opening having sidewalls that are coated with a dielectric material, the sidewalls having a slope associated therewith such that an area of the opening is larger at the second surface of the semiconductor layer than at the first surface of the semiconductor layer; depositing an electrically conductive material upon the tapered sidewalls and upon the exposed portion of the second surface of the dielectric layer; removing the substrate to expose the first surface of the dielectric layer; forming an opening through the dielectric layer, the opening being formed in registration with the opening through the semiconductor layer and exposing a portion of the electrically conductive material that was deposited upon the portion of the second surface of the dielectric layer; and depositing an electrically conductive material within the opening formed through the dielectric layer such that the electrically conductive material that was deposited within the opening through the semiconductor layer is electrically coupled to the electrically conductive material that is within the opening through the dielectric layer.
Claim 3
Dependent Claim
41 words
A method as set forth in claim 1 wherein the semiconductor layer is comprised of <100> silicon, and wherein the step of forming at least one opening through the semiconductor layer includes a step of etching the <100> silicon with KOH.
Claim 4
Dependent Claim
62 words
A method as set forth in claim 1 wherein the step of forming at least one opening through the semiconductor layer includes the initial steps of: forming a dielectric layer upon the second surface of the semiconductor layer; and opening an aperture through the dielectric layer, the aperture having an area that is a function of the thickness of the semiconductor layer.
Claim 5
Dependent Claim
98 words
A method as set forth in claim 1 wherein the semiconductor layer is comprised of <100> silicon that has a thickness in the range of approximately 10 micrometers to approximately 50 micrometers, and wherein the step of forming at least one opening through the semiconductor layer includes the steps of: forming an oxide layer upon the second surface of the <100> silicon layer; opening an aperture through the oxide layer, the aperture having a diameter that is at least approximately twice the thickness of the <100> silicon layer; and etching the <100> silicon with KOH through the aperture.
Claim 6
Dependent Claim
17 words
A method as set forth in claim 2 wherein the slope is approximately equal to 54.7 degrees.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1997-06-20 | 1997-12-20 | 1998-06-21 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-06-20 | 2001-12-20 | 2002-06-21 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-06-20 | 2005-12-20 | 2006-06-21 | $7700.00 | Window Closed / Lapsed |