Patent US5321700A successfully refreshed from Google Patents.
US5321700A
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High speed timing generator
Assignee: Teradyne Inc
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Filing: 1990-10-30
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Granted: 1994-06-14
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Expires: 2010-10-30
Abstract
Abstract A high speed timing generator including a pattern generator circuit, a plurality local generator circuits associated with respective nodes of a device under test, and a plurality of distribution paths. The pattern generator circuit has a high speed pattern generator which generates a high speed address and a divider circuit which divides the high speed address into a plurality of lower speed address patterns at a lower frequency. Each local generator circuit has a plurality of signal generator circuits which operate at the lower frequency of the lower speed address patterns and provide lower frequency signals and a high speed formatter circuit which uses the lower frequency signals to provide a high frequency signal. The plurality of distribution paths provide the lower speed address patterns to the local generator circuit.
Inventors
- 👤 Benjamin J. Brown
- 👤 Peter A. Reichert
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-03 10:15
CPC Classifications
G; G01; G01R; G01R31/00; G01R31/28; G01R31/317; G01R31/3181; G01R31/319; G01R31/31903; G01R31/31908; G01R31/3191; G01R31/31917; G01R31/31922; G01R31/31928; G06; G06F; G06F1/00; G06F1/02; G06F1/03; G06F1/0321; G06F17/00; G06F17/10; G06F17/17; G01R31/31919
Claims Analysis
Total Claims: 58
Claim 1
Independent Claim
152 words
An apparatus for generating a plurality of high frequency signals for use in testing a device under test comprising a pattern generator circuit, said pattern generator circuit including a high speed address pattern generator that generates high speed address patterns at a high frequency, and a divider circuit that is connected to receive said high speed address patterns and splits each said high speed address pattern into a plurality of associated lower speed address patterns at a lower frequency, a plurality of local generator circuits that are each connected to receive said associated lower speed address patterns and each generate a high frequency signal based on said associated lower speed address patterns for application to a respective node of said device under test, and a plurality of low speed distribution paths connected between said divider and said local generator circuits to provide said lower speed address patterns to said local generator circuits.
Claim 2
Independent Claim
152 words
An apparatus for generating a plurality of high frequency signals for use in testing a device under test comprising a pattern generator circuit, said pattern generator circuit including a high speed address pattern generator that generates high speed address patterns at a high frequency, and a divider circuit that is connected to receive said high speed address patterns and splits each said high speed address pattern into a plurality of associated lower speed address patterns at a lower frequency, a plurality of local generator circuits that are each connected to receive said associated lower speed address patterns and each generate a high frequency signal based on said associated lower speed address patterns for application to a respective node of said device under test, and a plurality of low speed distribution paths connected between said divider and said local generator circuits to provide said lower speed address patterns to said local generator circuits.
Claim 3
Dependent Claim
20 words
The apparatus of claim 1 wherein said divider circuit includes means for providing said lower speed address patterns in cycles.
Claim 4
Dependent Claim
21 words
The apparatus of claim 2 wherein said divider circuit includes means for providing said lower speed address patterns in a sequence.
Claim 5
Dependent Claim
35 words
The apparatus of claim 3 wherein said divider provides two lower speed address patterns, said two lower speed address patterns each having a frequency which is half the frequency of said higher speed address pattern.
Claim 6
Dependent Claim
37 words
The apparatus of claim 3 wherein said divider provides four lower speed address patterns, said four lower speed address patterns each having a frequency which is a quarter of the frequency of said higher speed address pattern.
Claim 7
Dependent Claim
23 words
The apparatus of claim 1 wherein said divider is configured to provide a certain lower speed address pattern upon receiving a reset signal.
Claim 8
Dependent Claim
17 words
The apparatus of claim 6 wherein said reset signal is received when said apparatus is initially turned-on.
Claim 9
Dependent Claim
23 words
The apparatus of claim 6 wherein said reset signal is received at the beginning of a burst of said high speed address patterns.
Claim 10
Dependent Claim
25 words
The apparatus of claim 8 wherein there are a plurality of bursts of high speed address patterns for a device under test by said apparatus.
Claim 11
Dependent Claim
23 words
The apparatus of claim 9 wherein there are between 10 and 200 bursts of high speed address patterns for said device under test.
Claim 12
Dependent Claim
50 words
The apparatus of claim 1 wherein each said local generator circuit includes a plurality of signal generator circuits configured to operate at said lower frequency and to provide lower frequency signals, and a high speed formatter configured to receive said lower frequency signals and to provide said high frequency signal.
Claim 13
Dependent Claim
98 words
The apparatus of claim 11 wherein, each said signal generator circuit includes a plurality of local memories each connected to a said distribution path to be addressed by addresses in a said lower speed address pattern, said memories storing timing information. a plurality of timing generators each connected to a respective said memory to receive said timing information read from said memory and generating timing generator information based upon said timing information, and a plurality of interpolator circuits each connected to a respective timing generator to receive said timing generator information and generating a said lower frequency signal.
Claim 14
Dependent Claim
25 words
The apparatus of claim 12 wherein said timing generator information is provided to said interpolator circuit using a clock signal generated by said interpolator circuit.
Claim 15
Dependent Claim
56 words
The apparatus of claim 12 wherein said timing generator information includes signal generator circuit further includes a match signal and a residue signal, said match signal being sued by said interpolator circuit to determine when to start generating said lower frequency signal, said residue signal being used to determine when to provide said lower frequency signal.
Claim 16
Dependent Claim
88 words
The apparatus of claim 1 wherein said divider circuit is configured to receive a first mode select input that selects between a plurality of modes of operation of said divider circuit, in a first of said plurality of modes of operation, said divider circuit receives said high-speed address patterns and provides said plurality of lower-speed address patterns at said lower frequency, and in a second of said plurality of modes of operation, said divider receives said high-speed address patterns and provides said high-speed address patterns as an output.
Claim 17
Dependent Claim
128 words
The apparatus of claim 1, wherein said divider circuit is configured to receive a second mode select input that selects between a plurality of modes of operation of said divider circuit, in a first of said plurality of modes of operation, said divider circuit receives said high-speed address patterns from said high-speed address pattern generator over a single path, in a second of said plurality of modes of operation, said divider circuit receives said high-speed address patterns from said high-speed address pattern generator over a first path, provides said high-speed address patterns at a first output, receives a second set of high-speed address patterns from a second high-speed address pattern generator over a second path, and provides said second set of high-speed address patterns at a second output.
Claim 18
Dependent Claim
223 words
A circuit for producing period information including an edge identification signal, said circuit being arranged for use in conjunction with a reference clock that produces a clock signal, said circuit comprising a plurality of period oscillators, each of said plurality of period oscillators comprising a summation circuit for receiving a plurality of period values representing a corresponding plurality of adjacent time periods, and for summing said period values to produce a summation output, and an edge selector circuit for receiving at least a most significant portion of said summation output, and for producing said edge identification signal, said edge identification signal identifying an edge of said clock signal, said edge being located an integral number of edges away from an edge previously identified by said edge selector circuit, said integral number being determined from at least said most significant portion of said summation output, said plurality of period oscillators being arranged in a manner such that each of a succession of period values representing a corresponding succession of adjacent time periods is received by each said summation circuit of each of said plurality of period oscillators, but each period value in said succession of period values is summed with differing combinations of other period values in said succession of period values by differing summation circuits of each of said plurality of period oscillators.
Claim 19
Dependent Claim
223 words
A circuit for producing period information including an edge identification signal, said circuit being arranged for use in conjunction with a reference clock that produces a clock signal, said circuit comprising a plurality of period oscillators, each of said plurality of period oscillators comprising a summation circuit for receiving a plurality of period values representing a corresponding plurality of adjacent time periods, and for summing said period values to produce a summation output, and an edge selector circuit for receiving at least a most significant portion of said summation output, and for producing said edge identification signal, said edge identification signal identifying an edge of said clock signal, said edge being located an integral number of edges away from an edge previously identified by said edge selector circuit, said integral number being determined from at least said most significant portion of said summation output, said plurality of period oscillators being arranged in a manner such that each of a succession of period values representing a corresponding succession of adjacent time periods is received by each said summation circuit of each of said plurality of period oscillators, but each period value in said succession of period values is summed with differing combinations of other period values in said succession of period values by differing summation circuits of each of said plurality of period oscillators.
Claim 20
Dependent Claim
66 words
A circuit in accordance with claim 17, wherein said edge selector circuit comprises a counter arranged to receive at least said most significant portion of said summation output, to count a number of clock cycles of said reference clock, said number corresponding to said most significant portion of said summation output, and, upon counting said number of said clock cycles, to produce said edge identification signal.
Claim 21
Dependent Claim
78 words
A circuit in accordance with claim 17, wherein said period information includes a residue signal, wherein each of said plurality of period oscillators further comprises a residue circuit for producing said residue signal representative of a residual time from said edge of said clock signal identified by said edge selector circuit, said residual time being determined from a summation of a least significant portion of said summation output and a previous residue signal produced by said residue circuit.
Claim 22
Dependent Claim
37 words
A circuit in accordance with claim 19, wherein each of said plurality of period oscillators further comprises a register connected to receive said summation output, said register producing an output that is received by said residue circuit.
Claim 23
Dependent Claim
15 words
A circuit in accordance with claim 17 wherein there are two of said period oscillators.
Claim 24
Dependent Claim
84 words
A circuit in accordance with claim 17 wherein each of said plurality of period oscillators comprises at least one pipeline-to-pipeline synchronizer for receiving period values and for outputting said period values on a first-in-first-out basis to said summation circuit at times determined by edges of said clock signal selected by said edge selector circuit, said pipeline-to-pipeline synchronizer receiving said period values at times determined by edges of said clock signal selected by an edge selector circuit of another of said plurality of period oscillators.
Claim 25
Dependent Claim
73 words
A circuit in accordance with claim 22, wherein each said pipeline-to-pipeline synchronizer of each of said plurality of period oscillators is arranged to receive a mode selection input that forces said pipeline-to-pipeline synchronizer to output period values of zero to said summation circuit when said mode selection input selects an independent operation mode in which one of said plurality of period oscillators operates independently of any other of said plurality of period oscillators.
Claim 26
Dependent Claim
115 words
A circuit in accordance with claim 17, further comprising default circuitry for resetting said plurality of period oscillators, said default circuitry being arranged to enable said summation circuits of said plurality of period oscillators to receive a plurality of default values instead of said plurality of period values, said default circuitry causing said default values to be received by said summation circuits in an order and manner such that each of said edge selector circuits of said plurality of period oscillators produces a signal that identifies an edge of said clock signal that is not identified by a signal produced by any other edge selector circuit of any other of said plurality of period oscillators.
Claim 27
Dependent Claim
20 words
A circuit in accordance with claim 24, wherein all of said plurality of default values are a same default value.
Claim 28
Dependent Claim
94 words
A circuit in accordance with claim 25, wherein said default circuitry is arranged to reset said plurality of period oscillators by applying a period value of zero to each of said plurality of oscillators, then applying said default value to said summation circuit of each of said plurality of period oscillators, and said summation circuits are arranged to receive said default value at differing numbers of inputs of each summation circuit during one cycle of operation of each period oscillator, and to receive said default value at every input during subsequent cycles of operation.
Claim 29
Dependent Claim
214 words
A circuit for producing period information including an edge identification signal, said circuit being arranged for use in conjunction with a reference clock that produces a clock signal, said circuit comprising a plurality of period oscillators, each of said plurality of period oscillators comprising a memory for receiving period addressed and for producing a corresponding plurality of period values, a summation circuit for receiving a plurality of period values and for summing said period values to produce a summation output, one of said period values being received from said memory and at least one other of said period values being received from a memory of another of said plurality of period oscillators, said plurality of period values being received from a memory of another of said plurality of period oscillators, said plurality of period values representing a corresponding plurality of adjacent time periods, and an edge selector circuit for receiving at least a most significant portion of said summation output, and for producing said edge identification signal, said edge identification signal identifying an edge of said clock signal, said edge being located an integral number of edges away from an edge previously identified by said edge selector circuit, said integral number being determined from at least said most significant portion of said summation output.
Claim 30
Dependent Claim
214 words
A circuit for producing period information including an edge identification signal, said circuit being arranged for use in conjunction with a reference clock that produces a clock signal, said circuit comprising a plurality of period oscillators, each of said plurality of period oscillators comprising a memory for receiving period addressed and for producing a corresponding plurality of period values, a summation circuit for receiving a plurality of period values and for summing said period values to produce a summation output, one of said period values being received from said memory and at least one other of said period values being received from a memory of another of said plurality of period oscillators, said plurality of period values being received from a memory of another of said plurality of period oscillators, said plurality of period values representing a corresponding plurality of adjacent time periods, and an edge selector circuit for receiving at least a most significant portion of said summation output, and for producing said edge identification signal, said edge identification signal identifying an edge of said clock signal, said edge being located an integral number of edges away from an edge previously identified by said edge selector circuit, said integral number being determined from at least said most significant portion of said summation output.
Claim 31
Dependent Claim
87 words
A circuit in accordance with claim 27, wherein said plurality of period oscillators are arranged in a manner such that each of a succession of period values representing a corresponding succession of adjacent time periods is received by each said summation circuit of each of said plurality of period oscillators, but each period value in said succession of period values is summed with differing combinations of other period values in said succession of period values by differing summation circuits of each of said plurality of period oscillators.
Claim 32
Dependent Claim
66 words
A circuit in accordance with claim 27, wherein said edge selector circuit comprises a counter arranged to receive at least said most significant portion of said summation output, to count a number of clock cycles of said reference clock, said number corresponding to said most significant portion of said summation output, and, upon counting said number of said clock cycles, to product said edge identification signal.
Claim 33
Dependent Claim
78 words
A circuit in accordance with claim 27, wherein said period information includes a residue signal, wherein each of said plurality of period oscillators further comprises a residue circuit for producing said residue signal representative of a residual time from said edge of said clock signal identified by said edge selector circuit, said residual time being determined from a summation of a least significant portion of said summation output and a previous residue signal produced by said residue circuit.
Claim 34
Dependent Claim
37 words
A circuit in accordance with claim 30, wherein each of said plurality of period oscillators further comprises a register connected to receive said summation output, said register producing an output that is received by said residue circuit.
Claim 35
Dependent Claim
15 words
A circuit in accordance with claim 27 wherein there are two of said period oscillators.
Claim 36
Dependent Claim
120 words
A circuit in accordance with claim 27 wherein each of said plurality of period oscillators comprises at least one pipeline-to-pipeline synchronizer for receiving said at least one other of said period values from said memory of said another of said plurality of period oscillators and for outputting said at least one other of said period values on a first-in-first-out basis to said summation circuit at a time determined by an edge of said clock signal selected by said edge selector circuit, said pipeline-to-pipeline synchronizer receiving said at least one other of said period values at a time determined by an edge of said clock signal selected by an edge selector circuit of said another of said plurality of period oscillators.
Claim 37
Dependent Claim
73 words
A circuit in accordance with claim 33, wherein each said pipeline-to-pipeline synchronizer of each of said plurality of period oscillators is arranged to receive a mode selection input that forces said pipeline-to-pipeline synchronizer to output period values of zero to said summation circuit when said mode selection input selects an independent operation mode in which one of said plurality of period oscillators operates independently of any other of said plurality of period oscillators.
Claim 38
Dependent Claim
113 words
A circuit in accordance with claim 27, further comprising default circuitry for resetting said plurality of period oscillators, said default circuitry being arranged to enable each said summation circuit of said plurality of period oscillators to receive a default value instead of a period value, said default circuitry causing default values to be received by said summation circuits in an order and manner such that each of said edge selector circuits of said plurality of period oscillators produces an edge identification signal that identifies an edge of said clock signal that is not identified by a signal produced by any other edge selector circuit of any other of said plurality of period oscillators.
Claim 39
Dependent Claim
18 words
A circuit in accordance with claim 35, wherein all of said default values are a same default value.
Claim 40
Dependent Claim
98 words
A circuit in accordance with claim 36, wherein said default circuitry is arranged to reset said plurality of period oscillators by applying a period value of zero to said summation circuit of each of said plurality of oscillators, then applying said default value to said summation circuit of each of said plurality of period oscillators, and said summation circuits are arranged to receive said default value at differing numbers of inputs of each summation circuit during one cycle of operation of each period oscillator, and to receive said default value at every input during subsequent cycles of operation.
Claim 41
Independent Claim
252 words
An apparatus for generating patterns, comprising a high-speed pattern generator that generates high-speed period addresses at a high frequency, a divider circuit that is connected to receive said high-speed period addresses and splits each said high speed address pattern tin to a plurality of lower-speed period addresses at a lower frequency, a circuit for producing period information including an edge identification signal, said circuit being arranged for use in conjunction with a reference clock that produces a clock signal, said circuit comprising a plurality of period oscillators, each of said plurality of period oscillators comprising a memory for receiving lower-speed period addresses from said divider circuit, and for producing a corresponding plurality of period values, a summation circuit for receiving a plurality of period values, one of said period values being received from said memory and at least one other of said period values being received from a memory of another of said plurality of period oscillators, said plurality of period values representing a corresponding plurality of adjacent time periods, and for summing said period values to provide a summation output, and an edge selector circuit for receiving at least a most significant portion of said summation output, and for producing said edge identification signal, said edge identification signal identifying an edge of said clock signal, said edge being located an integral number of edges away from an edge previously identified by said edge selector circuit, said integral number being determined from at least said most significant portion of said summation output.
Claim 42
Independent Claim
252 words
An apparatus for generating patterns, comprising a high-speed pattern generator that generates high-speed period addresses at a high frequency, a divider circuit that is connected to receive said high-speed period addresses and splits each said high speed address pattern tin to a plurality of lower-speed period addresses at a lower frequency, a circuit for producing period information including an edge identification signal, said circuit being arranged for use in conjunction with a reference clock that produces a clock signal, said circuit comprising a plurality of period oscillators, each of said plurality of period oscillators comprising a memory for receiving lower-speed period addresses from said divider circuit, and for producing a corresponding plurality of period values, a summation circuit for receiving a plurality of period values, one of said period values being received from said memory and at least one other of said period values being received from a memory of another of said plurality of period oscillators, said plurality of period values representing a corresponding plurality of adjacent time periods, and for summing said period values to provide a summation output, and an edge selector circuit for receiving at least a most significant portion of said summation output, and for producing said edge identification signal, said edge identification signal identifying an edge of said clock signal, said edge being located an integral number of edges away from an edge previously identified by said edge selector circuit, said integral number being determined from at least said most significant portion of said summation output.
Claim 43
Dependent Claim
89 words
An apparatus in accordance with claim 38 wherein each of said plurality of period oscillators is arranged in a manner such that each of a succession of period values representing a corresponding succession of adjacent time periods is received by each said summation circuit of each of said plurality of period oscillators, but each period value in said succession of period values is summed with differing combinations of other period values in said succession of period values by differing summation circuits of each of said plurality of period oscillators.
Claim 44
Dependent Claim
17 words
An apparatus in accordance with claim 38, wherein said divider circuit cyclically provides said lower-speed period addresses.
Claim 45
Dependent Claim
29 words
An apparatus in accordance with claim 40, wherein said divider circuit provides said lower-speed period addresses in a sequence, and said sequence is determined by said high-speed period addresses.
Claim 46
Dependent Claim
18 words
An apparatus in accordance with claim 41, wherein said divider circuit provides two lower-speed sequences of period addresses.
Claim 47
Dependent Claim
72 words
An apparatus in accordance with claim 38, wherein said edge selector circuit comprises a counter arranged to receive at least said most significant portion of said summation output, to count a number of clock cycles of said reference clock, said number corresponding to said most significant portion of said summation output, and, upon counting said number of said clock cycles, to produce said signal that identifies said edge of said clock signal.
Claim 48
Dependent Claim
70 words
A circuit in accordance with claim 38, wherein each of said plurality of period oscillators further comprises a residue circuit for producing a residue signal representative of a residual time from said edge of said clock signal identified by said edge selector circuit, said residual time being determined from a summation of a least significant portion of said summation output and a previous residue signal produced by said residue circuit.
Claim 49
Dependent Claim
37 words
A circuit in accordance with claim 44, wherein each of said plurality of period oscillators further comprises a register connected to receive said summation output, said register producing an output that is received by said residue circuit.
Claim 50
Dependent Claim
15 words
A circuit in accordance with claim 38 wherein there are two of said period oscillators.
Claim 51
Dependent Claim
120 words
A circuit in accordance with claim 38 wherein each of said plurality of period oscillators comprises at least one pipeline-to-pipeline synchronizer for receiving said at least one other of said period values from said memory of said another of said plurality of period oscillators and for outputting said at least one other of said period values on a first-in-first-out basis to said summation circuit at a time determined by an edge of said clock signal selected by said edge selector circuit, said pipeline-to-pipeline synchronizer receiving said at least one other of said period values at a time determined by an edge of said clock signal selected by an edge selector circuit of said another of said plurality of period oscillators.
Claim 52
Dependent Claim
73 words
A circuit in accordance with claim 47, wherein each said pipeline-to-pipeline synchronizer of each of said plurality of period oscillators is arranged to receive a mode selection input that forces said pipeline-to-pipeline synchronizer to output period values of zero to said summation circuit when said mode selection input selects an independent operation mode in which one of said plurality of period oscillators operates independently of any other of said plurality of period oscillators.
Claim 53
Dependent Claim
111 words
A circuit in accordance with claim 38, further comprising default circuitry for resetting said plurality of period oscillators, said default circuitry being arranged to enable each said summation circuit of said plurality of period oscillators to receive a default value instead of a period value, said default circuitry causing default values to be received by said summation circuits in an order and manner such that each of said edge selector circuits of said plurality of period oscillators produces a signal that identifies an edge of said clock signal that is not identified by a signal produced by any other edge selector circuit of any other of said plurality of period oscillators.
Claim 54
Dependent Claim
18 words
A circuit in accordance with claim 49, wherein all of said default values are a same default value.
Claim 55
Dependent Claim
98 words
A circuit in accordance with claim 50, wherein said default circuitry is arranged to reset said plurality of period oscillators by applying a period value of zero to said summation circuit of each of said plurality of oscillators, then applying said default value to said summation circuit of each of said plurality of period oscillators, and said summation circuits are arranged to receive said default value at differing numbers of inputs of each summation circuit during one cycle of operation of each period oscillator, and to receive said default value at every input during subsequent cycles of operation.
Claim 56
Dependent Claim
75 words
A circuit in accordance with claim 38, further comprising a plurality of timing generator and interpolation circuits, each of said plurality of timing generator and interpolation circuits being arranged to receive said signal produced by a said edge selector circuit of a corresponding one of said plurality of period oscillators and to produce a timing edge at a point in time determined at least in part by said signal produced by said edge selector circuit.
Claim 57
Dependent Claim
99 words
A circuit in accordance with claim 52, wherein each of said plurality of period oscillators further comprises a residue circuit for producing a residue signal representative of a residual time from said edge of said clock signal identified by said edge selector circuit, said residual time being determined from a summation of a least significant portion of said summation output and a previous residue signal produced by said residue circuit, and each of said plurality of timing generator and interpolation circuits delays said timing edge by said residual time represented by said residue signal produced by said residue circuit.
Claim 58
Dependent Claim
41 words
A circuit in accordance with claim 52, wherein said plurality of timing generator and interpolation circuits are arranged to apply each said timing edge produced by each of said plurality of timing generator and interpolation circuits to a device under test.
References Cited (Backward Citations)
US4500993A
Cited
US4727312A
Cited
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| 7.5 Years (Year 8) | 2001-06-13 | 2001-12-13 | 2002-06-14 | $3760.00 | Window Closed / Lapsed |
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