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US4727312A
Expired / Lapsed
US
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Circuit tester
Assignee: Genrad Inc
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Filing: 1985-12-23
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Granted: 1988-02-23
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Expires: 2005-12-23
Abstract
Abstract A tester (10) for testing an electronic circuit (22) has test terminals (18a-d) that are to be connected to the terminals (20a-d) of the circuit under test. The tester terminals (18a-d) are placed in the states required for testing by formatter circuits (32a-d) in accordance with state codes generated by state-code generators (24a-d). However, the state-code generators (24a-d) are not required to generate every code as quickly as those codes are needed by the formatters (32a-d), because first-in, first-out memory stacks (30a-d) are interposed between the state-code generators (24a-d) and the formatters (32a-d). This permits the state-code generators (24a-d) to employ relatively slow--and thus relatively inexpensive--memories (26).
Inventors
- 👤 Robert G. Fulks
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 18:41
CPC Classifications
G; G01; G01R; G01R31/00; G01R31/28; G01R31/317; G01R31/3181; G01R31/319; G01R31/31917; G01R31/31928; G01R31/31919; G01R31/31921
Claims Analysis
Total Claims: 3
Claim 1
Independent Claim
189 words
In a circuit tester, having a plurality of tester terminals for connection to terminals of a unit under test, for performing a test by placing the terminals in a sequence of terminal states, control circuitry for controlling the terminal states of the tester terminals to specify the test operations to be performed, the control circuitry comprising: A. a first-in, first-out memory for storing state codes applied thereto; B. an advance-time machine for generating state codes representing terminal states and for applying those state codes to the first-in, first-out memory; C. a real-time machine for fetching those state codes from the first-in, first-out memory, and for placing the tester terminals in the states represented by the fetched state codes concurrently with the application of state codes to the first-in, first-out memory, and with a timing independent of that with which the advance-time machine applies state codes to the memory, so that the real-time machine places the terminals in the states represented by the state codes that the advance-time machine generates, whereby the control circuitry can change terminal states at a rate different from that at which it generates state codes.
Claim 2
Dependent Claim
189 words
In a circuit tester, having a plurality of tester terminals for connection to terminals of a unit under test, for performing a test by placing the terminals in a sequence of terminal states, control circuitry for controlling the terminal states of the tester terminals to specify the test operations to be performed, the control circuitry comprising: A. a first-in, first-out memory for storing state codes applied thereto; B. an advance-time machine for generating state codes representing terminal states and for applying those state codes to the first-in, first-out memory; C. a real-time machine for fetching those state codes from the first-in, first-out memory, and for placing the tester terminals in the states represented by the fetched state codes concurrently with the application of state codes to the first-in, first-out memory, and with a timing independent of that with which the advance-time machine applies state codes to the memory, so that the real-time machine places the terminals in the states represented by the state codes that the advance-time machine generates, whereby the control circuitry can change terminal states at a rate different from that at which it generates state codes.
Claim 3
Dependent Claim
120 words
A circuit tester as recited in claim 1 wherein: A. the first-in, first-out memory includes an individual first-in, first-out stack associated with each tester terminal; B. the advance-time machine includes an individual state-code generator associated with each tester terminal for generating a sequence of state codes for its associated tester terminal and for applying those state codes to the individual first-in, first-out stack associated with that tester terminal; and C. the real-time machine includes a formatter associated with each tester terminal for fetching from the first-in, first-out stack associated with the same tester terminal the earliest state code applied thereto and not previously fetched and for placing its associated tester terminal in the state represented by the fetched state code.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1991-02-22 | 1991-08-24 | 1992-02-23 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1995-02-22 | 1995-08-24 | 1996-02-23 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1999-02-22 | 1999-08-24 | 2000-02-23 | $7700.00 | Window Closed / Lapsed |