Microcomputer having a dual port memory of supplying write data directly to an output

Claim 2

A microcomputer comprising an arithmetic logic unit and a memory unit coupled to said arithmetic logic unit through internal buses, wherein said microcomputer is formed on a single semicomputer substrate, said memory unit comprising: memory means for storing data including a plurality of memory cells, a plurality of first and second word lines, and a plurality of pairs of data lines, wherein each of said plurality of memory cells is respectively coupled to a first word line, a second word line and a pair of data lines; write means, coupled with said plurality of pairs of data lines, for writing write data, provided from said arithmetic logic unit, into selected ones of said plurality of memory cells; first decoder means for selecting one of said plurality of first word lines in accordance with first address signals supplied at inputs thereof; second decoder means for selecting one of said plurality of second word lines in accordance with second address signals supplied at inputs thereof; comparing means having inputs coupled to receive said first and second address signals and for outputting a coincidence signal when there is coincidence between the first and second address signals; bypass means for transferring said write data as read data without said write data passing through said plurality of pairs of data lines thereby bypassing said memory means; and data output means having inputs coupled to receive read data, corresponding to data read from said memory means, and said write data from said bypass means and having a control input, wherein said data output means outputs said write data when said coincidence signal is provided to said control input.

Claim 3

A microcomputer according to claim 1, wherein each of said plurality of memory cells includes a flip-flop circuit comprised of MOSFETs.

Claim 4

A microcomputer according to claim 2, wherein each flip-flop circuit includes a pair of CMOS inverters having cross-coupled input and output terminals.

Claim 5

A microcomputer according to claim 1, wherein said data input means includes a plurality of clocked inverters each of said plurality of clocked inverters has an input, an output and a control terminal, and said plurality of clocked inverters are divided into first and second groups of clocked inverters in which the inputs thereof are coupled to receive said write data and said read data, respectively, and in which the control terminals thereof are coupled to receive said coincidence signal and its logical complement, respectively.

Claim 6

A microcomputer according to claim 4, wherein said data output means further includes a data buffer having inputs commonly coupled to receive write data outputted from said clocked inverters of said first group or read data outputted from said clocked inverters of said second group.

Claim 7

A microcomputer comprising an arithmetic logic unit and a memory coupled to said arithmetic logic unit, wherein the microcomputer is formed on a single semiconductor chip, said memory comprising: memory means for storing data including a memory array having memory cell, a plurality of first word lines and a plurality of second word lines, a plurality of pairs of data lines and write means for providing potentials, in accordance with write data receive from said arithmetic logic unit, to said pairs of data lines, wherein each of said memory cells is coupled to a first word line, a second word line and a pair of data lines; first means for selecting one of said plurality of first word lines in accordance with first address signals supplied at inputs thereof, wherein when said one first word line is selected, the memory cells coupled thereto are supplied with write data, through said write means, from said arithmetic logic unit; second means for selecting one of said plurality of second word lines in accordance with second address signals supplied at inputs thereof, wherein when said one second word line is selected, the memory cell coupled thereto supply read data; comparing means having inputs coupled to receive said first and second address signals and an output for outputting a coincidence signal when there is coincidence between the first and second address signals; bypass means for transferring said write data as read data to respective inputs of third means, said bypass means being electrically isolated from said plurality of pairs of data lines and said plurality of memory cells; and wherein said third means has separate inputs coupled to receive read data corresponding to data read from said memory array and the write data from said bypass means, respectively, said third means having a control input coupled to the output of said comparing means for receiving said coincidence signal, and said third means in response to said coincidence signal at said control input outputting said write data as read data.

Claim 8

A microcomputer comprising an arithmetic logic unit and a memory coupled to said arithmetic logic unit, wherein the microcomputer is formed on a single semiconductor chip, said memory comprising: memory means for storing data including a memory array having memory cell, a plurality of first word lines and a plurality of second word lines, a plurality of pairs of data lines and write means for providing potentials, in accordance with write data receive from said arithmetic logic unit, to said pairs of data lines, wherein each of said memory cells is coupled to a first word line, a second word line and a pair of data lines; first means for selecting one of said plurality of first word lines in accordance with first address signals supplied at inputs thereof, wherein when said one first word line is selected, the memory cells coupled thereto are supplied with write data, through said write means, from said arithmetic logic unit; second means for selecting one of said plurality of second word lines in accordance with second address signals supplied at inputs thereof, wherein when said one second word line is selected, the memory cell coupled thereto supply read data; comparing means having inputs coupled to receive said first and second address signals and an output for outputting a coincidence signal when there is coincidence between the first and second address signals; bypass means for transferring said write data as read data to respective inputs of third means, said bypass means being electrically isolated from said plurality of pairs of data lines and said plurality of memory cells; and wherein said third means has separate inputs coupled to receive read data corresponding to data read from said memory array and the write data from said bypass means, respectively, said third means having a control input coupled to the output of said comparing means for receiving said coincidence signal, and said third means in response to said coincidence signal at said control input outputting said write data as read data.

Claim 9

A microcomputer according to claim 6, wherein said third means includes a data select circuit of at least one clocked inverter having a control terminal coupled to receive said coincidence signal.

Claim 10

A microcomputer according to claim 6, wherein said third means comprises a data select circuit including a plurality of clock inverters, each of said plurality of clocked inverters has an input, an output and a control terminal, and said plurality of clocked inverters are divided into first and second groups of clocked inverters in which the inputs thereof are coupled to receive said write data and said read data, respectively, and in which the control terminals thereof are coupled to receive said coincidence signal and its logical complement, respectively.

Claim 11

A microcomputer according to claim 6, wherein said first address signals are write address signals and said second address signals are read address signals.

Claim 12

A microcomputer according to claim 9, wherein each of said memory cells includes a flip-flop circuit comprised of MOSFETs.