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US5317705A
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Apparatus and method for TLB purge reduction in a multi-level machine system
Assignee: International Business Machines Corp
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Filing: 1993-08-26
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Granted: 1994-05-31
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Expires: 2013-08-26
Abstract
Abstract A system for reducing purging of a translation lookaside buffer (TLB) to reduce operating system overhead in a system running multiple levels of virtual machines. A system typically must purge TLB entries whenever an underlying page table entry is invalidated due to paging activity on the host machine, or an underlying guest machine. A system for reducing the number of cases in which guest translations are based on host page table entries is provided. Additional logic is supplied to analyze each invalidate page table entry (IPTE) instruction to minimize the extent of purging required as a result of that instruction. When the region relocate facility is in operation, or when no pageable TLB's have been constructed, only the entry corresponding to the page table entry to be invalidated need be purged. This limited purging reduces the overhead by reducing the time spent in purging and the time required in address translation to rebuild the TLB. This time saving results in increased performance in systems with multi-level guests.
Inventors
- 👤 Patrick M. Gannon
- 👤 Peter H. Gum
- 👤 Roger E. Hough
- 👤 Robert E. Murray
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 06:47
CPC Classifications
G; G06; G06F; G06F12/00; G06F12/02; G06F12/08; G06F12/10; G06F12/1027; G06F12/1036; G06F9/00; G06F9/06; G06F9/44; G06F9/455; G06F9/45533; G06F9/45558; G06F2009/45583; G06F2212/00; G06F2212/10; G06F2212/1016; G06F2212/68; G06F2212/683
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
236 words
A computer system having a real processor and a random access memory, the computer system having a host hypervisor operating with virtual machines, and guests operating in any address translation mode of: a virtual=fixed guest, a virtual=real guest and a pageable guest, the system comprising translation lookaside buffer means in the processor for storing guest-translated virtual addresses and associated absolute addresses provided for virtual machines executing at plural guest address translation levels, a region relocation facility (RRF) mode indicator which is set on when the memory is divided into fixed contiguous memory locations for use by different virtual=fixed guests, a pageable-guest-was-processed (PGWP) indicator associated with the buffer means, the PGWP indicator being set on when a pageable guest's address translation information is stored in any entry in the buffer means, and the PGWP indicator being set of when the buffer means is purged by invalidation of all entries in the buffer means, means for signalling to the buffer means an invalidation request provided by a program, the request containing a table index for locating entry(s) in the buffer means to be invalidated and indicating a particular translation level for the request, means responsive to the signalling means for invalidating all entries in the buffer means upon detecting predetermined combined settings of the PGWP indicator and the region relocation facility mode indicator, and the signalling means indicating a translation level other than a lowest guest translation level.
Claim 2
Dependent Claim
236 words
A computer system having a real processor and a random access memory, the computer system having a host hypervisor operating with virtual machines, and guests operating in any address translation mode of: a virtual=fixed guest, a virtual=real guest and a pageable guest, the system comprising translation lookaside buffer means in the processor for storing guest-translated virtual addresses and associated absolute addresses provided for virtual machines executing at plural guest address translation levels, a region relocation facility (RRF) mode indicator which is set on when the memory is divided into fixed contiguous memory locations for use by different virtual=fixed guests, a pageable-guest-was-processed (PGWP) indicator associated with the buffer means, the PGWP indicator being set on when a pageable guest's address translation information is stored in any entry in the buffer means, and the PGWP indicator being set of when the buffer means is purged by invalidation of all entries in the buffer means, means for signalling to the buffer means an invalidation request provided by a program, the request containing a table index for locating entry(s) in the buffer means to be invalidated and indicating a particular translation level for the request, means responsive to the signalling means for invalidating all entries in the buffer means upon detecting predetermined combined settings of the PGWP indicator and the region relocation facility mode indicator, and the signalling means indicating a translation level other than a lowest guest translation level.
Claim 3
Dependent Claim
68 words
A computer system for operating plural levels of virtual machines (guests) as defined in claim 1, further comprising means responsive to the signalling means for only invalidating entry(s) located in the buffer means by the table index provided by the signalling means upon the existence of particular predetermined combined states of the PGWP indicator, the region relocation facility mode indicator and the signalling means indicating any translation level.
Claim 4
Dependent Claim
141 words
A computer system for operating plural levels of virtual machines (guests) as defined in claim 1, further comprising a plurality of processors provided in the computer system, each processor having a respective buffer means for containing address translations of all translation levels, means for the host hypervisor and any of the guests to execute a buffer invalidation instruction on any one of the processors to invalidate all entries in the buffer means of the associated processor and to invalidate only entries in the buffer means located by the table index in the manner defined in claim 1, and means for transferring invalidation signals from the processor executing the buffer invalidation instruction to other processors in the computer system for the other processors to invalidate any corresponding buffer entry(s) located by the table index in any other processor in the computer system.
Claim 5
Dependent Claim
52 words
A computer system for operating plural levels of virtual machines (guests) as defined in claim 1, further comprising: means for actuating the invalidation means to invalidate all entries in the buffer means associated with the processor when the PGWP indicator is set on and the region relocation mode indicator is set off.
Claim 6
Dependent Claim
61 words
A computer system for operating plural levels of virtual machines (guests) as defined in claim 1, further comprising: means for actuating the invalidation means to invalidate all entries in the buffer means associated with the processor when both the PGWP mode indicator and the region relocate mode indicator are set on for a virtual=fixed guest which is allowed to have guests.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1997-05-30 | 1997-11-29 | 1998-05-31 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-05-30 | 2001-11-29 | 2002-05-31 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-05-30 | 2005-11-29 | 2006-05-31 | $7700.00 | Window Closed / Lapsed |