Leading one/zero bit detector for floating point operation

Claim 3

A method according to claim 1 wherein said step of detecting is performed simultaneously with and in parallel to said operation in said arithmetic unit.

Claim 4

A method acording to claim 2 wherein said steps of applying, detecting and aligning are all performed in a single-chip integrated circuit device containing said floating point processor.

Claim 5

A floating point processor, comprising: (a) an arithmetic unit, and means for applying a first n-bit floating point operand and a second n-bit floating point operand to inputs of said arithmetic unit to perform a floating point operation on said first n-bit floating point operand and said second n-bit floating point operand and generate a floating point result at an output of the arithmetic unit; (b) a leading one position or leading zero position detection circuit including: (i) means for scanning each bit position of both of said first n-bit floating point operand and said second n-bit floating point operand from left to right to detect a trigger condition: A.sub.i+1 XOR B.sub.i+1 =0 where A is the first n-bit floating point operand, B is the second n-bit floating point operand, A i or B i is the value of a bit in position i in A or B, A i+1 or B i+1 is the value of a bit one position to the left of A i or B i , and XOR is an Exclusive-OR operator; (ii) means for continuing to scan from left to right, and, if said floating point result is a positive value, detecting a next bit position j where: [A.sub.j, B.sub.j ]=NOT[0,0] where j<i, A j or B j is the value of a bit in position j in A or B, and designating said bit position j where [A j , B j ]=NOT[0,0] as the leading one position in the floating point result, or, if said floating point result is a negative value, detecting a next bit position j where: [A.sub.j, B.sub.j ]=NOT[1,1] and designating said bit position j where [A j , B j ]=NOT[1,1] as the leading zero position in the floating point result; (c) and means for aligning said floating point result to said leading one position if the floating point result is a positive value or to said leading zero position if said floating point result is a negative value.

Claim 6

A floating point processor, comprising: (a) an arithmetic unit, and means for applying a first n-bit floating point operand and a second n-bit floating point operand to inputs of said arithmetic unit to perform a floating point operation on said first n-bit floating point operand and said second n-bit floating point operand and generate a floating point result at an output of the arithmetic unit; (b) a leading one position or leading zero position detection circuit including: (i) means for scanning each bit position of both of said first n-bit floating point operand and said second n-bit floating point operand from left to right to detect a trigger condition: A.sub.i+1 XOR B.sub.i+1 =0 where A is the first n-bit floating point operand, B is the second n-bit floating point operand, A i or B i is the value of a bit in position i in A or B, A i+1 or B i+1 is the value of a bit one position to the left of A i or B i , and XOR is an Exclusive-OR operator; (ii) means for continuing to scan from left to right, and, if said floating point result is a positive value, detecting a next bit position j where: [A.sub.j, B.sub.j ]=NOT[0,0] where j<i, A j or B j is the value of a bit in position j in A or B, and designating said bit position j where [A j , B j ]=NOT[0,0] as the leading one position in the floating point result, or, if said floating point result is a negative value, detecting a next bit position j where: [A.sub.j, B.sub.j ]=NOT[1,1] and designating said bit position j where [A j , B j ]=NOT[1,1] as the leading zero position in the floating point result; (c) and means for aligning said floating point result to said leading one position if the floating point result is a positive value or to said leading zero position if said floating point result is a negative value.

Claim 7

Apparatus according to claim 4 wherein said leading one or leading zero detection circuit operates simultaneously with and in parallel to said operation in said arithmetic unit.

Claim 8

Apparatus according to claim 5 wherein said arithmetic unit, said detection circuit, and said means for aligning are all contained in a single-chip integrated circuit device containing said floating point processor.

Claim 11

A method according to claim 7 wherein said step of scanning is performed simultaneously with and in parallel to operate in an adder unit.

Claim 12

A leading one position or leading zero position detection circuit for a floating point operation comprising: (i) means for scanning each bit position of both a first n-bit floating point operand and a second n-bit floating point operand from left to right to detect a trigger condition: A.sub.i+1 XOR B.sub.i+1 =0 where A is the first n-bit floating point operand, B is the second n-bit floating point operand, A i or B i is the value of a bit in position i in A or B, A i+1 or B i+1 is the value of a bit one position to the left of A i or B i , and XOR is an Exclusive-OR operator; (ii) mans for continuing to scan from left to right, and, if a floating point result of said floating point operation is a positive value, detecting a next bit position j where: [A.sub.j,B.sub.j ]=NOT[0,0] where j<i, A j or B j is the value of a bit in position j in A or B, and designating said bit position j where [A j ,B j ]=NOT[0,0] as the leading one position in the floating point result, or, if said floating point result of said floating point operation is a negative value, detecting a next bit position j where: [A.sub.j B.sub.j ]=NOT[1,1] and designating said bit position j where [A j B j ]=NOT[1,1] as the leading zero position in the floating point result.

Claim 13

A leading one position or leading zero position detection circuit for a floating point operation comprising: (i) means for scanning each bit position of both a first n-bit floating point operand and a second n-bit floating point operand from left to right to detect a trigger condition: A.sub.i+1 XOR B.sub.i+1 =0 where A is the first n-bit floating point operand, B is the second n-bit floating point operand, A i or B i is the value of a bit in position i in A or B, A i+1 or B i+1 is the value of a bit one position to the left of A i or B i , and XOR is an Exclusive-OR operator; (ii) mans for continuing to scan from left to right, and, if a floating point result of said floating point operation is a positive value, detecting a next bit position j where: [A.sub.j,B.sub.j ]=NOT[0,0] where j<i, A j or B j is the value of a bit in position j in A or B, and designating said bit position j where [A j ,B j ]=NOT[0,0] as the leading one position in the floating point result, or, if said floating point result of said floating point operation is a negative value, detecting a next bit position j where: [A.sub.j B.sub.j ]=NOT[1,1] and designating said bit position j where [A j B j ]=NOT[1,1] as the leading zero position in the floating point result.

Claim 14

Apparatus according to claim 9 wherein said leading one or leading zero detection circuit operates simultaneously with and in parallel to an operation in an arithmetic unit.

Claim 15

Apparatus according to claim 10 wherein said arithmetic unit and said detection circuit are all contained in a single-chip integrated circuit device.

Claim 18

The method of claim 12, wherein the step of detecting a leading one position further comprises the steps of: (a) scanning each bit position of both of said first n-bit floating point operand and said second n-bit floating point operand from left to right to detect a trigger condition: A.sub.i+1 XOR B.sub.i+1 =0 where A is the first n-bit floating point operand, B is the second n-bit floating point operand, A i or B i is the value of a bit in position i in A or B, A i+1 or B i+1 is the value of a bit one position to the left of A i or B i , and XOR is an Exclusive-OR operator; and (b) upon detecting said trigger condition, continuing to scan from left to right and detecting a next bit position j where: [A.sub.j, B.sub.j ]=NOT[0,0] where j<i, A j or B j is the value of a bit in position j in A or B, and designating said bit position j as the leading one position.

Claim 19

The method of claim 12 wherein the step of detecting a leading zero further comprises the steps of: (a) scanning each bit position of both of said first n-bit floating point operand and said second n-bit floating point operand from left to right to detect a trigger condition: A.sub.i+1 XOR B.sub.i+1 =0 where A is the first n-bit floating point operand, B is the second n-bit floating point operand, A i or B i is the value of a bit in position i in A or B, A i+1 or B i+1 is the value of a bit one position to the left of A i or B i , and XOR is an Exclusive-OR operator; and (b) upon detecting said trigger condition, continuing to scan from left to right, and detecting a next bit position j where: [A.sub.j, B.sub.j ]=NOT[1,1] where j<i, A j or B j is the value of a bit in position j in A or B, and designating said bit position j as the leading zero position.

Claim 20

A floating point processor, comprising: (a) an arithmetic unit for performing a floating point operation on operands to generate a floating point result at an output of said arithmetic unit; (b) means for applying a first n-bit floating point operand and a second n-bit floating point operand to the arithmetic unit; (c) means for detecting a leading one position in parallel with the floating point operation performed by the arithmetic unit; (d) means for detecting a leading zero position in parallel with the floating point operation performed by the arithmetic unit; (e) means for determining whether the floating point result is a positive value or a negative value; (f) means for selecting the leading one position if the floating point result is a positive value or the leading zero position if the floating point result is negative value; and (g) means for aligning said floating point result to said leading one position if the floating point result is a positive value or to said leading zero position if said floating point result is a negative value.

Claim 21

A floating point processor, comprising: (a) an arithmetic unit for performing a floating point operation on operands to generate a floating point result at an output of said arithmetic unit; (b) means for applying a first n-bit floating point operand and a second n-bit floating point operand to the arithmetic unit; (c) means for detecting a leading one position in parallel with the floating point operation performed by the arithmetic unit; (d) means for detecting a leading zero position in parallel with the floating point operation performed by the arithmetic unit; (e) means for determining whether the floating point result is a positive value or a negative value; (f) means for selecting the leading one position if the floating point result is a positive value or the leading zero position if the floating point result is negative value; and (g) means for aligning said floating point result to said leading one position if the floating point result is a positive value or to said leading zero position if said floating point result is a negative value.

Claim 22

The floating point processor of claim 15 wherein the means for detecting a leading zero position further comprises: (a) means for scanning each bit position of both of said first n-bit floating point operand and said second n-bit floating point operand from left to right to detect a trigger condition: A.sub.i+1 XOR B.sub.i+1 =0 where A is the first n-bit floating point operand, B is the second n-bit floating point operand, A i or B i is the value of a bit in position i in A or B, A i+1 or B i+1 is the value of a bit one position to the left of A i or B i , and XOR is an Exclusive-OR operator; and (b) upon detecting said trigger condition, means for continuing to scan from left to right and detecting a next bit position j where: [A.sub.j, B.sub.j ]=NOT[0,0] where j<i, A j or B j is the value of a bit in position j in A or B, and for designating said bit position j as the leading one position.

Claim 23

The floating point processor of claim 15 wherein the means for detecting a leading zero position further comprises: (a) means for scanning each bit position of both of said first n-bit floating point operand and said second n-bit floating point operand from left to right to detect a trigger condition: A.sub.i+1 XOR B.sub.i+ =0 where A is the first n-bit floating point operand, B is the second n-bit floating point operand, A i or B i is the value of a bit in position i in A or B, A i+1 or B i+1 is the value of a bit one position to the left of A i or B i , and XOR is an Exclusive-OR operator; and (b) upon detecting said trigger condition, means for continuing to scan from left to right, and detecting a next bit position j where: [A.sub.j, B.sub.j ]=NOT[1,1] where j<i, A j or B j is the value of a bit in position j in A or B, and for designating said bit position j as the leading zero position.