Level converter with delay circuitry used to increase switching speed

Claim 2

A level converter for converting an input signal of a first logic type level received at an input node into an output signal of a second logic type level, comprising: an output node for supplying the output signal; first means responsive to said input signal for setting said output node at a level of a first potential; second means responsive to said input signal for setting said output node at a level of a second potential; delay means for delaying a signal at said output node; and control means responsive to a delay signal received from said delay means, for controlling the magnitude of a resistance between said output node and said second potential, wherein said second means includes latch means for latching a signal potential at said output node, and wherein said control means includes means responsive to said delay signal, for changing the magnitude of a resistance between said latch means and said second potential.

Claim 3

A level converter for converting an input signal of a first logic type level received at an input node into an output signal of a second logic type level, comprising: an output node for supplying the output signal; first means responsive to said input signal for setting said output node at a level of a first potential; second means responsive to said input signal for setting said output node at a level of a second potential; delay means for delaying a signal at said output node; and control means responsive to a delay signal received from said delay means, for controlling the magnitude of a resistance between said output node and said second potential, wherein said second means includes latch means for latching a signal potential at said output node, and wherein said control means includes means responsive to said delay signal, for changing the magnitude of a resistance between said output node and said latch means.

Claim 4

A level converter for converting an input signal of a first logic type level received at an input node into an output signal of a second logic type level, comprising: an output node for supplying the output signal; first means responsive to said input signal for setting said output node at a level of a first potential; second means responsive to said input signal for setting said output node at a level of a second potential; delay means for delaying a signal at said output node; and control means responsive to a delay signal received from said delay means, for controlling the magnitude of a resistance between said output node and said second potential, wherein said second means includes latch means for latching a signal potential at said output node, and wherein said control means includes means responsive to said delay signal, for changing the magnitude of a resistance between said output node and said latch means.

Claim 5

A level converter for converting an input signal of a first logic type level received at an input node into an output signal of a second logic type level, comprising: an output node for supplying the output signal; first means responsive to said input signal for setting said output node at a level of a first potential; second means responsive to said input signal for setting said output node at a level of a second potential; delay means for delaying a signal at said output node; and control means responsive to a delay signal received from said delay means, for controlling the magnitude of a resistance between said output node and said second potential, wherein said second means includes: a first field effect transistor provided between said input node and a first node having a gate receiving a predetermined reference potential, a second field effect transistor having one conduction terminal coupled to receive said second potential and a gate connected to said output node, a third field effect transistor having one conduction terminal coupled to receive said second potential and a gate connected to said first node, and wherein said delay means includes: a first buffer for inverting and amplifying a signal at said output node, and a second buffer for inverting and amplifying an output signal of said first buffer, and wherein said control means includes: a fourth field effect transistor provided between said first node and said second field effect transistor and having a gate receiving the output signal of said first buffer, and a fifth field effect transistor provided between said output node and said third field effect transistor and having a gate receiving an output signal of said second buffer.

Claim 6

A level converter for converting an input signal of a first logic type level received at an input node into an output signal of a second logic type level, comprising: an output node for supplying the output signal; first means responsive to said input signal for setting said output node at a level of a first potential; second means responsive to said input signal for setting said output node at a level of a second potential; delay means for delaying a signal at said output node; and control means responsive to a delay signal received from said delay means, for controlling the magnitude of a resistance between said output node and said second potential, wherein said second means includes: a first field effect transistor provided between said input node and a first node having a gate receiving a predetermined reference potential, a second field effect transistor having one conduction terminal coupled to receive said second potential and a gate connected to said output node, a third field effect transistor having one conduction terminal coupled to receive said second potential and a gate connected to said first node, and wherein said delay means includes: a first buffer for inverting and amplifying a signal at said output node, and a second buffer for inverting and amplifying an output signal of said first buffer, and wherein said control means includes: a fourth field effect transistor provided between said first node and said second field effect transistor and having a gate receiving the output signal of said first buffer, and a fifth field effect transistor provided between said output node and said third field effect transistor and having a gate receiving an output signal of said second buffer.

Claim 7

A level converter according to claim 3, wherein said control means further includes: a first resistance means provided between said first node and said second field effect transistor and having a resistance substantially the same as an on-resistance of said fourth field effect transistor, and a second resistance means provided between said output node and said third field effect transistor having a resistance substantially the same as an on-resistance said fifth field effect transistor.

Claim 8

A level converter according to claim 4, wherein said first resistance means includes a field effect transistor connected in parallel with said fourth field effect transistor and having a gate connected to receive said first potential.

Claim 9

A level converter according to claim 4, wherein said second resistance means includes a field effect transistor connected in parallel with said fifth field effect transistor and having a gate connected to receive said second potential.

Claim 10

A level converter for converting an input signal of a first logic type level received at an input node into an output signal of a second logic type level, comprising: an output node for supplying the output signal; first means responsive to said input signal for setting said output node at a level of a first potential; second means responsive to said input signal for setting said output node at a level of a second potential; delay means for delaying a signal at said output node; and control means responsive to a delay signal received from said delay means, for controlling the magnitude of a resistance between said output node and said second potential, wherein said second means includes: a first field effect transistor having one conduction terminal connected to said input node, another conduction terminal connected to a first node, and a gate connected to receive a predetermined potential, a second field effect transistor having one conduction terminal connected to said first node, another conduction terminal connected to a second node, and a gate connected to said output node, and a third field effect transistor having one conduction terminal connected to said output node, another conduction terminal connected to a third node, and wherein said delay means includes: a first buffer for inverting and amplifying a signal at said output node, and a second buffer for inverting and amplifying an output of said first buffer, and wherein said control means includes: a fourth field effect transistor having one conduction terminal connected to said second node, another conduction terminal connected to receive said second potential, and a gate connected to receive the output of said first buffer, and a fifth field effect transistor having one conduction terminal connected to said third node, another conduction terminal connected to receive said second potential, and a gate connected to receive an output of said second buffer.

Claim 11

A level converter for converting an input signal of a first logic type level received at an input node into an output signal of a second logic type level, comprising: an output node for supplying the output signal; first means responsive to said input signal for setting said output node at a level of a first potential; second means responsive to said input signal for setting said output node at a level of a second potential; delay means for delaying a signal at said output node; and control means responsive to a delay signal received from said delay means, for controlling the magnitude of a resistance between said output node and said second potential, wherein said second means includes: a first field effect transistor having one conduction terminal connected to said input node, another conduction terminal connected to a first node, and a gate connected to receive a predetermined potential, a second field effect transistor having one conduction terminal connected to said first node, another conduction terminal connected to a second node, and a gate connected to said output node, and a third field effect transistor having one conduction terminal connected to said output node, another conduction terminal connected to a third node, and wherein said delay means includes: a first buffer for inverting and amplifying a signal at said output node, and a second buffer for inverting and amplifying an output of said first buffer, and wherein said control means includes: a fourth field effect transistor having one conduction terminal connected to said second node, another conduction terminal connected to receive said second potential, and a gate connected to receive the output of said first buffer, and a fifth field effect transistor having one conduction terminal connected to said third node, another conduction terminal connected to receive said second potential, and a gate connected to receive an output of said second buffer.

Claim 12

A level converter according to claim 7, wherein said control means further includes a first resistance means connected in parallel with said fourth field effect transistor and having a resistance substantially the same as an on-resistance of said fourth field effect transistor, and a second resistance means connected in parallel with said fifth field effect transistor and having a resistance substantially the same as an on-resistance said fifth field effect transistor.

Claim 13

A level converter according to claim 8, wherein said first resistance means comprises a field effect transistor having one conduction terminal connected to said second node, a gate connected to receive said first potential and another conduction terminal connected to receive said second potential.

Claim 14

A level converter according to claim 8, wherein said second resistance means comprises a field effect transistor having one conduction terminal connected to said output node, a gate connected to receive said first potential, and another conduction terminal connected to receive said second potential.

Claim 15

A level converter for converting an input signal of a first logic type level received at an input node into an output signal of a second logic type level, comprising: an output node for supplying the output signal; first means responsive to said input signal for setting said output node at a level of a first potential; second means responsive to said input signal for setting said output node at a level of a second potential; delay means for delaying a signal at said output node; and control means responsive to a delay signal received from said delay means, for controlling the magnitude of a resistance between said output node and said second potential, wherein said second means includes a first current path between said input node and a node supplying said second potential, for providing a current flow responsive to said input signal, and a current path between said output node and the node supplying said second potential in a current mirror configuration with said first current path, and wherein said control means includes: means responsive to the delay signal for changing a resistance value of at least one of said first and second current paths.

Claim 16

A level converter for converting an input signal of a first logic type level received at an input node into an output signal of a second logic type level, comprising: an output node for supplying the output signal; first means responsive to said input signal for setting said output node at a level of a first potential; second means responsive to said input signal for setting said output node at a level of a second potential; delay means for delaying a signal at said output node; and control means responsive to a delay signal received from said delay means, for controlling the magnitude of a resistance between said output node and said second potential, wherein said second means includes a first current path between said input node and a node supplying said second potential, for providing a current flow responsive to said input signal, and a current path between said output node and the node supplying said second potential in a current mirror configuration with said first current path, and wherein said control means includes: means responsive to the delay signal for changing a resistance value of at least one of said first and second current paths.

Claim 17

A level converter according to claim 11, wherein said delay means comprises a first buffer for inverting and amplifying a signal at said output node, and wherein said first current path includes a first field effect transistor having one conduction terminal connected to said input node, another conduction terminal connected to a first node, and a gate connected to receive a predetermined reference potential, a second field effect transistor having one conduction terminal connected to receive said second potential, another conduction terminal connected to a second node, and a gate connected to said first node for determining an amount of current flow through said second current path, and wherein said control means includes a field effect transistor having one conduction terminal connected to said first node, and another conduction terminal connected to said second node, and a gate connected to receive an output of said first buffer.

Claim 18

A level converter according to claim 12, wherein said control means further includes a resistance means connected between said first and second nodes and having a large resistance.

Claim 19

A level converter according to claim 13, wherein said resistance means comprises a field effect transistor having one conduction terminal connected to said first node, a gate connected to receive said first potential, and another conduction terminal connected to said second node.

Claim 20

A level converter according to claim 12, wherein said delay means further includes a second buffer for inverting and amplifying an output of said first buffer, and wherein said second current path includes a third field effect transistor having one conduction terminal connected to receive said second potential, a gate connected to said first node, and another conduction terminal connected to a third node, and wherein said control means further includes a fourth field effect transistor having one conduction terminal connected to said output node, another conduction terminal connected to said third node, and a gate connected to receive an output of said second buffer.

Claim 21

A level converter according to claim 15, wherein said control means further includes a resistance means connected between said third node and said output node in parallel with said fourth field effect transistor and having a resistance substantially the same as an on-resistance of said fourth field effect transistor.

Claim 22

A level converter according to claim 16, wherein said resistance means comprises a field effect transistor having one conduction terminal connected to said output node, a gate connected to receive said first potential, and another conduction terminal connected to said third node.

Claim 23

A level converter for converting an input signal of a first logic type level received at an input node into an output signal of a second logic type level, comprising: an output node for supplying the output signal; first means responsive to said input signal for setting said output node at a level of a first potential; second means responsive to said input signal for setting said output node at a level of a second potential; delay means for delaying a signal at said output node; and control means responsive to a delay signal received from said delay means, for controlling the magnitude of a resistance between said output node and said second potential, wherein said second means includes: a first field effect transistor responsive to an input signal complementary to the input signal applied to said first means for charging a first node at a level of the first potential, a second field effect transistor having one conduction terminal connected to a second node, a gate connected to said first node, and another conduction terminal connected to receive a second potential, and a third field effect transistor having one conduction terminal connected to said output node, a gate connected to said first node, and another conduction terminal connected to receive said second potential, and wherein said delay means includes: a first buffer for buffering a signal at said output node, and wherein said control means includes: a fourth field effect transistor having one conduction terminal connected to said first node, another conduction terminal connected to said second node, and a gate connected to receive an output of said buffer means.

Claim 24

A level converter for converting an input signal of a first logic type level received at an input node into an output signal of a second logic type level, comprising: an output node for supplying the output signal; first means responsive to said input signal for setting said output node at a level of a first potential; second means responsive to said input signal for setting said output node at a level of a second potential; delay means for delaying a signal at said output node; and control means responsive to a delay signal received from said delay means, for controlling the magnitude of a resistance between said output node and said second potential, wherein said second means includes: a first field effect transistor responsive to an input signal complementary to the input signal applied to said first means for charging a first node at a level of the first potential, a second field effect transistor having one conduction terminal connected to a second node, a gate connected to said first node, and another conduction terminal connected to receive a second potential, and a third field effect transistor having one conduction terminal connected to said output node, a gate connected to said first node, and another conduction terminal connected to receive said second potential, and wherein said delay means includes: a first buffer for buffering a signal at said output node, and wherein said control means includes: a fourth field effect transistor having one conduction terminal connected to said first node, another conduction terminal connected to said second node, and a gate connected to receive an output of said buffer means.

Claim 25

A level converter according to claim 18, wherein said control means further includes a resistance means connected between said first and second nodes in parallel with said fourth field effect transistor and having a resistance substantially the same as an on-resistance of said fourth field effect transistor.

Claim 26

A level converter for converting an input signal of a first logic type level received at an input node into an output signal of a second logic type level, comprising: an output node for supplying the output signal; first means responsive to said input signal for setting said output node at a level of a first potential; second means responsive to said input signal for setting said output node at a level of a second potential; delay means for delaying a signal at said output node; and control means responsive to a delay signal received from said delay means, for controlling the magnitude of a resistance between said output node and said second potential, wherein said first means includes: a first field effect transistor responsive to a signal received at a first input node for charging a first output node to the first potential, and a second field effect transistor responsive to a signal received at a second input node for charging a second output node to the first potential, the signal at the first input node being complementary to the signal at the second input node, and wherein said second means includes: a third field effect transistor responsive to the signal at the second input node for charging a first node to the first potential, a fourth field effect transistor having one conduction terminal connected to a second node, a gate connected to said first node, and another conduction terminal connected to receive a second potential, a fifth field effect transistor having one conduction terminal connected to said first output node, a gate connected to said said first node, and another conduction terminal connected to receive the second potential, a sixth field effect transistor responsive to the signal at the first input node for charging a third node to the first potential, a seventh field effect transistor having one conduction terminal connected to a fourth node, a gate connected to the third node, and another conduction terminal connected to receive the second potential, and an eighth field effect transistor having one conduction terminal connected to the second output node, a gate connected to the third node, and another conduction terminal connected to receive the second potential, and wherein said delay means includes: a first buffer for buffering the signal at said first output node, and wherein said control means includes: a ninth field effect transistor having one conduction terminal connected to said first node, a gate connected to receive an output of said first buffer, and another conduction terminal connected to the second node, and a tenth field effect transistor having one conduction terminal connected to the third node, a gate connected to receive an output of said second buffer, and another conduction terminal connected to the fourth node.

Claim 27

A level converter for converting an input signal of a first logic type level received at an input node into an output signal of a second logic type level, comprising: an output node for supplying the output signal; first means responsive to said input signal for setting said output node at a level of a first potential; second means responsive to said input signal for setting said output node at a level of a second potential; delay means for delaying a signal at said output node; and control means responsive to a delay signal received from said delay means, for controlling the magnitude of a resistance between said output node and said second potential, wherein said first means includes: a first field effect transistor responsive to a signal received at a first input node for charging a first output node to the first potential, and a second field effect transistor responsive to a signal received at a second input node for charging a second output node to the first potential, the signal at the first input node being complementary to the signal at the second input node, and wherein said second means includes: a third field effect transistor responsive to the signal at the second input node for charging a first node to the first potential, a fourth field effect transistor having one conduction terminal connected to a second node, a gate connected to said first node, and another conduction terminal connected to receive a second potential, a fifth field effect transistor having one conduction terminal connected to said first output node, a gate connected to said said first node, and another conduction terminal connected to receive the second potential, a sixth field effect transistor responsive to the signal at the first input node for charging a third node to the first potential, a seventh field effect transistor having one conduction terminal connected to a fourth node, a gate connected to the third node, and another conduction terminal connected to receive the second potential, and an eighth field effect transistor having one conduction terminal connected to the second output node, a gate connected to the third node, and another conduction terminal connected to receive the second potential, and wherein said delay means includes: a first buffer for buffering the signal at said first output node, and wherein said control means includes: a ninth field effect transistor having one conduction terminal connected to said first node, a gate connected to receive an output of said first buffer, and another conduction terminal connected to the second node, and a tenth field effect transistor having one conduction terminal connected to the third node, a gate connected to receive an output of said second buffer, and another conduction terminal connected to the fourth node.

Claim 28

A level converter according to claim 20, wherein said control means further includes a first resistance element connected between said first said second nodes in parallel with the ninth field effect transistor, and a second resistance element connected between said third and fourth nodes in parallel with said tenth field effect transistor.

Claim 29

A level converter according to claim 21, wherein each of said first and second resistance elements comprises a field effect transistor having a gate connected to receive a first potential, said first and second resistance elements having an on-resistance substantially the same as the on-resistance said ninth and tenth field effect transistors, respectively.

Claim 30

A level converter for converting an input signal of a first logic type level received at an input node into an output signal of a second logic type level, comprising: an output node for supplying the output signal; first means responsive to said input signal for setting said output node at a level of a first potential; second means responsive to said input signal for setting said output node at a level of a second potential; delay means for delaying a signal at said output node; and control means responsive to a delay signal received from said delay means, for controlling the magnitude of a resistance between said output node and said second potential, wherein said first means includes: a first field effect transistor responsive to a signal received at a first output node, for charging a first output node to a level of the first potential, and a second field effect transistor responsive to a signal at a second input node, for charging a second output node to a level of the first potential, the signal at the first input node being complementary to the signal at the second input node, and wherein said second means includes: a third field effect transistor having one conduction terminal connected to the first output node, a gate connected to receive the signal at the first input node, and another conduction terminal connected to a first node, a fourth field effect transistor having one conduction terminal connected to a second node, a gate connected to the second output node, and another conduction terminal connected to receive a second potential, a fifth field effect transistor having one conduction terminal connected to the second output node, a gate connected to the second input node, and another conduction terminal connected to a third node, and a sixth field effect transistor having one conduction terminal connected to a fourth node, a gate connected to the first output node, and another conduction terminal connected to receive the second potential and wherein said delay means includes: a first buffer for buffering the signal at said second output node, and a second buffer for buffering the signal at said first output node, and wherein said control means includes: a seventh field effect transistor having one conduction terminal connected to a first node, a gate connected to receive an output of the second buffer, and another conduction terminal connected to the second node, and an eighth field effect transistor having one conduction terminal connected to the third node, a gate connected to receive an output of the first buffer, and another conduction terminal connected to the fourth node.

Claim 31

A level converter for converting an input signal of a first logic type level received at an input node into an output signal of a second logic type level, comprising: an output node for supplying the output signal; first means responsive to said input signal for setting said output node at a level of a first potential; second means responsive to said input signal for setting said output node at a level of a second potential; delay means for delaying a signal at said output node; and control means responsive to a delay signal received from said delay means, for controlling the magnitude of a resistance between said output node and said second potential, wherein said first means includes: a first field effect transistor responsive to a signal received at a first output node, for charging a first output node to a level of the first potential, and a second field effect transistor responsive to a signal at a second input node, for charging a second output node to a level of the first potential, the signal at the first input node being complementary to the signal at the second input node, and wherein said second means includes: a third field effect transistor having one conduction terminal connected to the first output node, a gate connected to receive the signal at the first input node, and another conduction terminal connected to a first node, a fourth field effect transistor having one conduction terminal connected to a second node, a gate connected to the second output node, and another conduction terminal connected to receive a second potential, a fifth field effect transistor having one conduction terminal connected to the second output node, a gate connected to the second input node, and another conduction terminal connected to a third node, and a sixth field effect transistor having one conduction terminal connected to a fourth node, a gate connected to the first output node, and another conduction terminal connected to receive the second potential and wherein said delay means includes: a first buffer for buffering the signal at said second output node, and a second buffer for buffering the signal at said first output node, and wherein said control means includes: a seventh field effect transistor having one conduction terminal connected to a first node, a gate connected to receive an output of the second buffer, and another conduction terminal connected to the second node, and an eighth field effect transistor having one conduction terminal connected to the third node, a gate connected to receive an output of the first buffer, and another conduction terminal connected to the fourth node.

Claim 32

A level converter according to claim 23, wherein said control means further includes: a first resistance element connected between said first and second nodes in parallel with the seventh field effect transistor and having a resistance substantially the same as an on-resistance of said seventh field effect transistor, and a second resistance element connected between said third and fourth nodes in parallel with the eighth field effect transistor and having a resistance substantially the same as an on-resistance of said eighth field effect transistor.

Claim 33

A level converter according to claim 24, wherein each of said first and second resistance elements comprises a field effect transistor having a gate connected to receive the first potential, said first and second resistance elements having an on-resistance substantially the same as the on-resistance of said seventh and eighth field effect transistors, respectively.