I/O cell for programmable logic device providing latched, unlatched, and fast inputs

Claim 2

An input/output (I/O) cell for interconnecting an I/O pad with an array of logic blocks in a programmable logic device in both a clocked and unclocked mode comprising a first multiplexing means having an input and a plurality of outputs, said first multiplexing means selectively connecting said input through one of said outputs to an array of logic array blocks through an internal bus of said PLD, latch means driven by a clock and coupled to said I/O pad and to said first multiplexing means for providing a clocked output to said I/O pad and clocked inputs to said first multiplexing means, and interconnecting means for directly connecting said I/O pad to at least one logic block without passing through said latch means and said first multiplexing means for fast input of selected signals from an external source with said external source directly driving said at least one of logic block.

Claim 3

An input/output (I/O) cell for interconnecting an I/O pad with internal circuitry in a programmable logic device (PLD) comprising a first multiplexing means having an input and a plurality of outputs, said first multiplexing means selectively connecting said input through one of said outputs to an array of logic array blocks through an internal bus of said PLD, latch means driven by a clock and coupled to said I/O pad and to said first multiplexing means for providing a clocked output to said I/O pad and clocked inputs to said first multiplexing means, a second multiplexing means having a plurality of inputs and an output for selectively connecting said I/O pad and said latch means to said input of said first multiplexing means, third multiplexing means having a plurality of inputs and an output for selectively connecting said I/O pad and an output of said first multiplexing means to said latch means, fourth multiplexing means having a plurality of inputs and an output for selectively connecting said latch means and said first multiplexing means to said I/O pad, and means for directly connecting said I/O pad to selected logic array blocks without passing through said latch means and said first multiplexing means.

Claim 4

An input/output (I/O) cell for interconnecting an I/O pad with internal circuitry in a programmable logic device (PLD) comprising a first multiplexing means having an input and a plurality of outputs, said first multiplexing means selectively connecting said input through one of said outputs to an array of logic array blocks through an internal bus of said PLD, latch means driven by a clock and coupled to said I/O pad and to said first multiplexing means for providing a clocked output to said I/O pad and clocked inputs to said first multiplexing means, a second multiplexing means having a plurality of inputs and an output for selectively connecting said I/O pad and said latch means to said input of said first multiplexing means, third multiplexing means having a plurality of inputs and an output for selectively connecting said I/O pad and an output of said first multiplexing means to said latch means, fourth multiplexing means having a plurality of inputs and an output for selectively connecting said latch means and said first multiplexing means to said I/O pad, and means for directly connecting said I/O pad to selected logic array blocks without passing through said latch means and said first multiplexing means.

Claim 5

The input/output cell as defined in claim 2 and further including a first buffer for connecting said I/O pad to said third multiplexing means and a second buffer connecting said fourth multiplexing means to said I/O pad.

Claim 6

The input/output cell as defined by claim 3 wherein said second buffer comprises a tristate device.

Claim 7

The input/output cell as defined by claim 4 wherein said means for directly connecting said I/O pad to selected logic array blocks is driven by an external source.

Claim 8

The I/O cell as defined by claim 5 wherein said logic array block includes a multiplexer connected to said fast input line.

Claim 9

The I/O cell as defined by claim 2 wherein said means for directly connecting said I/O pad to selected logic array blocks is driven by an external source.

Claim 10

An input/output (I/O) cell for interconnecting an I/O pad with internal circuitry in a programmable logic device (PLD) comprising a first multiplexing means having an input and a plurality of outputs, said first multiplexing means selectively connecting said input through one of said outputs to an array of logic array blocks through an internal bus of said PLD, latch means driven by a clock and coupled to said I/O pad and to said first multiplexing means for providing a clocked output to said I/O pad and clocked inputs to said first multiplexing means, and means for directly connecting said I/O pad to selected logic array blocks without passing through said latch means and said first multiplexing means including at least one fuse link for partitioning said means for directly connecting said I/O pad into segments thereby reducing resistance and capacitance if all segments are not used.

Claim 11

An input/output (I/O) cell for interconnecting an I/O pad with internal circuitry in a programmable logic device (PLD) comprising a first multiplexing means having an input and a plurality of outputs, said first multiplexing means selectively connecting said input through one of said outputs to an array of logic array blocks through an internal bus of said PLD, latch means driven by a clock and coupled to said I/O pad and to said first multiplexing means for providing a clocked output to said I/O pad and clocked inputs to said first multiplexing means, and means for directly connecting said I/O pad to selected logic array blocks without passing through said latch means and said first multiplexing means including at least one fuse link for partitioning said means for directly connecting said I/O pad into segments thereby reducing resistance and capacitance if all segments are not used.

Claim 12

The input/output cell as defined by claim 8 wherein said array of logic array blocks are interconnected through a bus to said I/O cell, said bus including fuse links for partitioning said bus into segments if all of the bus is not used.