Buffer circuit using capacitors to control the slow rate of a driver transistor

Claim 2

A buffer circuit comprising: a first potential source for supplying a potential of a first level, a second potential source for supplying a potential of a second level, an output element coupled to said first potential source and an output node, said output element having a control electrode and said output element being responsive to a signal applied to said control electrode for driving said output node to said first level, a first capacitive element having one electrode coupled to said first potential source and the other electrode coupled to said control electrode, a second capacitive element having one electrode and another electrode, said one electrode of said second capacitive element being coupled to said second potential source, shorting means activated in response to a signal of said second level provided to an input node for shorting said one electrode and said other electrode of said first capacitive element and shorting said first electrode and said other electrode of said second capacitive elements, connecting means activated in response to a signal of said first level provided to said input node for connecting said other electrode of said second capacitive element to said control electrode of said output element, delay means for delaying a signal applied to said input node for a predetermined time, and coupling means activated in response to a signal of said first level from said delay means for coupling said control electrode to said second potential source, said coupling means being activated after inactivation of said shorting means and activation of said connecting means.

Claim 3

A buffer circuit comprising: a first potential source for supplying a potential of a first level, a second potential source for supplying a potential of a second level, an output element coupled to said first potential source and an output node, said output element having a control electrode and said output element being responsive to a signal applied to said control electrode for driving said output node to said first level, a first capacitive element having one electrode coupled to said first potential source and the other electrode coupled to said control electrode, a second capacitive element having one electrode and another electrode, said one electrode of said second capacitive element being coupled to said second potential source, shorting means activated in response to a signal of said second level provided to an input node for shorting said one electrode and said other electrode of said first capacitive element and shorting said first electrode and said other electrode of said second capacitive element, connecting means activated in response to a signal of said first level provided to said input node for connecting said other electrode of said second capacitive element to said control electrode of said output element, potential detection means for detecting whether the potential of said output node has reached a predetermined potential level between said first level and said second level, and coupling means responsive to the potential detecting means detecting that the potential reaches the predetermined potential for coupling said control electrode of said output element to said second potential source.

Claim 4

A buffer circuit comprising: a first potential source for supplying a potential of a first level, a second potential source for supplying a potential of a second level, an output element coupled to said first potential source and an output node, said output element having a control electrode and said output element being responsive to a signal applied to said control electrode for driving said output node to said first level, a first capacitive element having one electrode coupled to said first potential source and the other electrode coupled to said control electrode, a second capacitive element having one electrode and another electrode, said one electrode of said second capacitive element being coupled to said second potential source, shorting means activated in response to a signal of said second level provided to an input node for shorting said one electrode and said other electrode of said first capacitive element and shorting said first electrode and said other electrode of said second capacitive element, connecting means activated in response to a signal of said first level provided to said input node for connecting said other electrode of said second capacitive element to said control electrode of said output element, potential detection means for detecting whether the potential of said output node has reached a predetermined potential level between said first level and said second level, and coupling means responsive to the potential detecting means detecting that the potential reaches the predetermined potential for coupling said control electrode of said output element to said second potential source.

Claim 5

A buffer circuit having an input node for receiving a signal and an output node for providing a signal, comprising: a first potential source for supplying a potential of a first level, a second potential source for supplying a potential of a second level, a first switching element coupled to said first potential source and an output node, said first switching element having a control electrode and said first switching element being responsive to a signal applied to said control electrode for driving said output node to said first level, a first capacitive element having one electrode coupled to said first potential source and the other electrode coupled to said control electrode, a second capacitive element having one electrode and another electrode, said one electrode of said second capacitive element being coupled to said second potential source, a second switching element provided in parallel with said first capacitive element, responsive to a signal applied to said input node for selectively shorting said one electrode and said other electrode of said first capacitive element, a third switching element provided in parallel with said second capacitive element, responsive to a signal applied to aid input node for selectively shorting said one electrode and said other electrode of said second capacitive element, a fourth switching element provided between said other electrode of said second capacitive element and said control electrode, responsive to a signal applied to said input node for selectively connecting said other electrode of said second capacitive element to said control electrode, delay means for delaying a signal applied to said input node for a predetermined time, and a fifth switching element responsive to an output of said delay means for selectively connecting said control electrode to said second potential source.

Claim 6

A buffer circuit having an input node for receiving a signal and an output node for providing a signal, comprising: a first potential source for supplying a potential of a first level, a second potential source for supplying a potential of a second level, a first switching element coupled to said first potential source and an output node, said first switching element having a control electrode and said first switching element being responsive to a signal applied to said control electrode for driving said output node to said first level, a first capacitive element having one electrode coupled to said first potential source and the other electrode coupled to said control electrode, a second capacitive element having one electrode and another electrode, said one electrode of said second capacitive element being coupled to said second potential source, a second switching element provided in parallel with said first capacitive element, responsive to a signal applied to said input node for selectively shorting said one electrode and said other electrode of said first capacitive element, a third switching element provided in parallel with said second capacitive element, responsive to a signal applied to aid input node for selectively shorting said one electrode and said other electrode of said second capacitive element, a fourth switching element provided between said other electrode of said second capacitive element and said control electrode, responsive to a signal applied to said input node for selectively connecting said other electrode of said second capacitive element to said control electrode, delay means for delaying a signal applied to said input node for a predetermined time, and a fifth switching element responsive to an output of said delay means for selectively connecting said control electrode to said second potential source.

Claim 7

A buffer circuit having an input node for receiving an input signal and an output node for providing a signal, comprising: a first potential source for supplying a potential of a first level, a second potential source for supplying a potential of a second level, a first switching element coupled to said first potential source and an output node, said first switching element having a control electrode and said first switching element being responsive to a signal applied to said control electrode for driving said output node to said first level, a first capacitive element having one electrode coupled to said first potential source and the other electrode coupled to said control electrode, a second capacitive element having one electrode and another electrode, said one electrode of said second capacitive element being coupled to said second potential source, a second switching element provided in parallel with said first capacitive element, responsive to a signal applied to said input node for selectively shorting said one electrode and said other electrode of said first capacitive element, a third switching element provided in parallel with said second capacitive element, responsive to a signal applied to said input node for selectively shorting said one electrode and said other electrode of said second capacitive element, a fourth switching element provided between said other electrode of said second capacitive element and said control electrode of said first switching element, responsive to a signal applied to said input node for selectively connecting said other electrode of said second capacitive element to said control electrode, potential detecting means for detecting whether the potential of said output node has reached a predetermined potential between said first level and said second level, and a fifth switching element responsive to an output of said potential detecting means for connecting said control electrode and said second potential source.

Claim 8

A buffer circuit having an input node for receiving an input signal and an output node for providing a signal, comprising: a first potential source for supplying a potential of a first level, a second potential source for supplying a potential of a second level, a first switching element coupled to said first potential source and an output node, said first switching element having a control electrode and said first switching element being responsive to a signal applied to said control electrode for driving said output node to said first level, a first capacitive element having one electrode coupled to said first potential source and the other electrode coupled to said control electrode, a second capacitive element having one electrode and another electrode, said one electrode of said second capacitive element being coupled to said second potential source, a second switching element provided in parallel with said first capacitive element, responsive to a signal applied to said input node for selectively shorting said one electrode and said other electrode of said first capacitive element, a third switching element provided in parallel with said second capacitive element, responsive to a signal applied to said input node for selectively shorting said one electrode and said other electrode of said second capacitive element, a fourth switching element provided between said other electrode of said second capacitive element and said control electrode of said first switching element, responsive to a signal applied to said input node for selectively connecting said other electrode of said second capacitive element to said control electrode, potential detecting means for detecting whether the potential of said output node has reached a predetermined potential between said first level and said second level, and a fifth switching element responsive to an output of said potential detecting means for connecting said control electrode and said second potential source.

Claim 9

A buffer circuit having an input node for receiving a signal and an output node for providing a signal, comprising: a first potential source for supplying a potential of a first level, a second potential source for supplying a potential of a second level, a first field effect transistor coupled to said first potential source and an output node, said first field effect transistor having a control electrode and being responsive to a signal applied to said control electrode for supplying current and voltage from said first potential source, a bipolar type transistor responsive to an output from said first field effect transistor for driving said output node to said first level, a first capacitive element having one electrode coupled to said first potential source, and the other electrode coupled to said control electrode of said first field effect transistor, a second capacitive element having one electrode and another electrode, said one electrode of said second capacitive element being connected to said second potential source, a second field effect transistor provided in parallel with said first capacitive element, responsive to a signal applied to said input node for shorting said first electrode and said other electrode of said first capacitive element, a third field effect transistor provided in parallel with said second capacitive element, responsive to a signal applied to said input node for shorting said one electrode and said other electrode of said second capacitive element, a fourth field effect transistor responsive to a signal applied to said input node for coupling said other electrode of said second capacitive element to said control electrode of said first field effect transistor, wherein said third field effect transistor and said fourth field effect transistor are turned on and off in a complementary manner, delay means for delaying a signal applied to said input node for a predetermined time, and a fifth field effect transistor responsive to an output of said delay means for coupling said control electrode of said first field effect transistor to said second potential source.

Claim 10

A buffer circuit having an input node for receiving a signal and an output node for providing a signal, comprising: a first potential source for supplying a potential of a first level, a second potential source for supplying a potential of a second level, a first field effect transistor coupled to said first potential source and an output node, said first field effect transistor having a control electrode and being responsive to a signal applied to said control electrode for supplying current and voltage from said first potential source, a bipolar type transistor responsive to an output from said first field effect transistor for driving said output node to said first level, a first capacitive element having one electrode coupled to said first potential source, and the other electrode coupled to said control electrode of said first field effect transistor, a second capacitive element having one electrode and another electrode, said one electrode of said second capacitive element being connected to said second potential source, a second field effect transistor provided in parallel with said first capacitive element, responsive to a signal applied to said input node for shorting said first electrode and said other electrode of said first capacitive element, a third field effect transistor provided in parallel with said second capacitive element, responsive to a signal applied to said input node for shorting said one electrode and said other electrode of said second capacitive element, a fourth field effect transistor responsive to a signal applied to said input node for coupling said other electrode of said second capacitive element to said control electrode of said first field effect transistor, wherein said third field effect transistor and said fourth field effect transistor are turned on and off in a complementary manner, delay means for delaying a signal applied to said input node for a predetermined time, and a fifth field effect transistor responsive to an output of said delay means for coupling said control electrode of said first field effect transistor to said second potential source.

Claim 11

A buffer circuit having an input node for receiving a signal and an output node for providing a signal, comprising: a first potential source for supplying a potential of a first level, a second potential source for supplying a potential of a second level, a first field effect transistor coupled to said first potential source and a first node, said first field effect transistor having a control electrode and being responsive to a signal applied to said control electrode for driving said first node to said first level, a bipolar type transistor responsive to a signal on said first node for coupling said output node to said second potential source, a first capacitive element provided between said second potential source and the control electrode of said first field effect transistor, a first switching element provided in parallel with said first capacitive element, responsive to a signal applied to said input node for shorting said first capacitive element, a second capacitive element having one electrode and another electrode, said one electrode of said second capacitive element being coupled to said first potential source, a second switching element provided in parallel with said second capacitive element, responsive to s a signal applied to said input node for shorting said one electrode and said other electrode of said second capacitive element, a third switching element responsive to a signal applied to said input node for coupling said other electrode of said second capacitive element to said control electrode of said field effect transistor, wherein said third switching element and said second switching element are turned on and off in a complementary manner, delay means for delaying a signal applied to said input node for a predetermined time, and a fourth switching element responsive to an output of said delay means for shorting said control electrode of said first field effect transistor and said first potential source.

Claim 12

A buffer circuit having an input node for receiving a signal and an output node for providing a signal, comprising: a first potential source for supplying a potential of a first level, a second potential source for supplying a potential of a second level, a first field effect transistor coupled to said first potential source and a first node, said first field effect transistor having a control electrode and being responsive to a signal applied to said control electrode for driving said first node to said first level, a bipolar type transistor responsive to a signal on said first node for coupling said output node to said second potential source, a first capacitive element provided between said second potential source and the control electrode of said first field effect transistor, a first switching element provided in parallel with said first capacitive element, responsive to a signal applied to said input node for shorting said first capacitive element, a second capacitive element having one electrode and another electrode, said one electrode of said second capacitive element being coupled to said first potential source, a second switching element provided in parallel with said second capacitive element, responsive to s a signal applied to said input node for shorting said one electrode and said other electrode of said second capacitive element, a third switching element responsive to a signal applied to said input node for coupling said other electrode of said second capacitive element to said control electrode of said field effect transistor, wherein said third switching element and said second switching element are turned on and off in a complementary manner, delay means for delaying a signal applied to said input node for a predetermined time, and a fourth switching element responsive to an output of said delay means for shorting said control electrode of said first field effect transistor and said first potential source.

Claim 13

A buffer circuit having an input node for receiving a signal and an output node for providing a signal, comprising: a first potential source for supplying a potential of a first level, a field effect transistor coupled to said first potential source and a first node, said field effect transistor having a control electrode, and being responsive to a signal applied to said control electrode for driving said first node to said first level, a bipolar type transistor responsive to a signal on said first node for coupling said output node to said second potential source, a first capacitive element provided between said first potential source and said control electrode, a first switching element responsive to a signal applied to said input node for shorting said first capacitive element, a second capacitive element having one electrode and another electrode, said one electrode of said second capacitive element being connected to said second potential source, a second switching element responsive to a signal applied to said input node for shorting said second capacitive element, a third switching element responsive t a signal applied to said input node for connecting said other electrode of said second capacitive element and said control electrode of said field effect transistor, wherein said third switching element is turned on and off in a complementary manner with said first and second switching elements, potential detecting means for detecting whether the potential of said output node has reached a predetermined potential between said first level and said second level, and a fourth switching element responsive to an output of said potential detecting means for coupling said control electrode of said field effect transistor and said second potential source.

Claim 14

A buffer circuit having an input node for receiving a signal and an output node for providing a signal, comprising: a first potential source for supplying a potential of a first level, a field effect transistor coupled to said first potential source and a first node, said field effect transistor having a control electrode, and being responsive to a signal applied to said control electrode for driving said first node to said first level, a bipolar type transistor responsive to a signal on said first node for coupling said output node to said second potential source, a first capacitive element provided between said first potential source and said control electrode, a first switching element responsive to a signal applied to said input node for shorting said first capacitive element, a second capacitive element having one electrode and another electrode, said one electrode of said second capacitive element being connected to said second potential source, a second switching element responsive to a signal applied to said input node for shorting said second capacitive element, a third switching element responsive t a signal applied to said input node for connecting said other electrode of said second capacitive element and said control electrode of said field effect transistor, wherein said third switching element is turned on and off in a complementary manner with said first and second switching elements, potential detecting means for detecting whether the potential of said output node has reached a predetermined potential between said first level and said second level, and a fourth switching element responsive to an output of said potential detecting means for coupling said control electrode of said field effect transistor and said second potential source.

Claim 15

A buffer circuit having an input node for receiving a signal and an output node for providing a signal, comprising: a first potential source for supplying a potential of a first level, a second potential source for supplying a potential of a second level, a first field effect transistor coupled to said first potential source and a first node, said first field effect transistor having a control electrode and being responsive to a signal applied to said control electrode for for driving said first node to said first level, a bipolar type transistor responsive to a signal on said first node for coupling said output node and said second potential source, a first capacitive element provided between said second potential source and the control electrode of said field effect transistor, a first switching element responsive to a signal applied to said input node for shorting said first capacitive element, a second capacitive element having one electrode and another electrode, said one electrode of said second capacitive element being coupled to said first potential source, a second switching element responsive to a signal applied to said input node for shorting said second capacitive element, a third switching element responsive to a signal applied to said input node for coupling said other electrode of said second capacitive element to said control electrode of said field effect transistor, wherein said third switching element is turned on and off in a complementary manner with said first and second switching elements, potential detecting means for detecting whether the potential of said output node has reached a predetermined potential level, and a fourth switching element responsive to an output of said potential detecting means for coupling said control electrode of said field effect transistor to said first potential source.

Claim 16

A buffer circuit having an input node for receiving a signal and an output node for providing a signal, comprising: a first potential source for supplying a potential of a first level, a second potential source for supplying a potential of a second level, a first field effect transistor coupled to said first potential source and a first node, said first field effect transistor having a control electrode and being responsive to a signal applied to said control electrode for for driving said first node to said first level, a bipolar type transistor responsive to a signal on said first node for coupling said output node and said second potential source, a first capacitive element provided between said second potential source and the control electrode of said field effect transistor, a first switching element responsive to a signal applied to said input node for shorting said first capacitive element, a second capacitive element having one electrode and another electrode, said one electrode of said second capacitive element being coupled to said first potential source, a second switching element responsive to a signal applied to said input node for shorting said second capacitive element, a third switching element responsive to a signal applied to said input node for coupling said other electrode of said second capacitive element to said control electrode of said field effect transistor, wherein said third switching element is turned on and off in a complementary manner with said first and second switching elements, potential detecting means for detecting whether the potential of said output node has reached a predetermined potential level, and a fourth switching element responsive to an output of said potential detecting means for coupling said control electrode of said field effect transistor to said first potential source.

Claim 19

A method according to claim 9, wherein said connecting step includes the steps of delaying the signal at said input node by a predetermined time, and connecting the control gate to the second potential level in response to such delayed signal.

Claim 20

A method according to claim 9, wherein said connecting step includes the steps of detecting whether or not a signal at said output node reaches a predetermined potential level, and connecting the control gate to the second potential level in response to detection of reaching said predetermined potential.

Claim 21

A method according to claim 9, wherein said output drive element includes an insulated gate type transistor having said control gate, and a bipolar type transistor, and wherein said method further comprises the step of driving said bipolar type transistor in response to an output of said insulated gate type transistor, for driving said output node.

Claim 22

A method according to claim 9, wherein said output drive element comprises an insulated gate type field effect transistor driving the output node.