US5120992A
Expired / Lapsed
US
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CMOS output driver with transition time control circuit
Assignee: National Semiconductor Corp
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Filing: 1991-07-03
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Granted: 1992-06-09
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Expires: 2011-07-03
Abstract
Abstract A single resistance permits a CMOS driver to have output devices that controllably transition "fast off-slow on" and which are not simultaneously on while the driver switches states. The driver's output and supply currents contain reduced harmonics. The resistance is coupled to the gates of the output stage PMOS-NMOS devices, and forms an RC circuit with the intrinsic capacitance at the gates, extending the turn-on transition of the gate drive voltages. Each output device then turns on relatively slowly, but turns off normally. The output current transition times are essentially determined by the resistance and intrinsic capacitances. The resistance is implemented using polysilicon or diffusion, and preferably has a magnitude ten times the on-channel resistance of the input PMOS and NMOS devices driving the output stage. Because the resistance and intrinsic capacitances are essentially temperature and power supply voltage independent, and but slightly process dependent, the current output transition times can be controlled despite CMOS parameter variations. A 3-state embodiment of the CMOS buffer uses parallel coupled PMOS-NMOS devices to switchably couple in the resistance between both output gates when the enable signal is high. Second input PMOS and NMOS devices, connected in parallel across the first input PMOS and NMOS devices, turn on across the first input devices when the enable signal is low. A high enable signal enables the driver circuit, while a low enable signal uncouples the resistance and turns off both output PMOS and NMOS devices, putting the circuit's output in a high impedance state.
Inventors
- 👤 William E. Miller
- 👤 Franklin S. Ho
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 18:59
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/003; H03K19/00346; H03K19/00361
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
211 words
An integrated circuit CMOS 3-state driver, comprising: an input port which receives an input signal, an enable port which receives an enable signal, and an output port which provides an output signal; a CMOS inverter including an output PMOS device and an output NMOS device coupled in series between first and second power sources, said PMOS and NMOS output devices each including a gate and having a drain coupled to said output port; delay means, including a resistor switchably coupled between said input port and said gates of said PMOS and NMOS output devices, for driving each said output device on more slowly than off; said resistor forming an RC delay circuit in conjunction with intrinsic capacitance present at said gates of said PMOS and NMOS output devices; and enabling means, including a switch coupled in series with said resistor between the enable port and said gates, for enabling said output devices when said enable signal is at a predefined voltage level; wherein said switch is coupled to said enable port so that said enable signal opens and closes said switch; whereby said output signal at said output port has increased transition times and reduced harmonic content compared to an output signal generated by a CMOS driver without said delay means.
Claim 2
Dependent Claim
211 words
An integrated circuit CMOS 3-state driver, comprising: an input port which receives an input signal, an enable port which receives an enable signal, and an output port which provides an output signal; a CMOS inverter including an output PMOS device and an output NMOS device coupled in series between first and second power sources, said PMOS and NMOS output devices each including a gate and having a drain coupled to said output port; delay means, including a resistor switchably coupled between said input port and said gates of said PMOS and NMOS output devices, for driving each said output device on more slowly than off; said resistor forming an RC delay circuit in conjunction with intrinsic capacitance present at said gates of said PMOS and NMOS output devices; and enabling means, including a switch coupled in series with said resistor between the enable port and said gates, for enabling said output devices when said enable signal is at a predefined voltage level; wherein said switch is coupled to said enable port so that said enable signal opens and closes said switch; whereby said output signal at said output port has increased transition times and reduced harmonic content compared to an output signal generated by a CMOS driver without said delay means.
Claim 3
Dependent Claim
19 words
The CMOS 3-state driver of claim 1, wherein said resistor has a resistance between 1 KΩ and 10 KΩ.
Claim 4
Dependent Claim
186 words
The CMOS 3-state driver of claim 1, wherein said delay means and enabling means together comprise an input PMOS device, said resistor, said switch, and an input NMOS device coupled in series between said first and second power sources; said input PMOS and NMOS devices each including a gate coupled to said input port; said input NMOS device having a drain coupled to said resistor and to said gate of said output NMOS device; and said input PMOS device having a drain coupled to said resistor and to said gate of said output PMOS device; whereby, when said enable signal closes said switch and said input signal turns said input PMOS device off, said intrinsic capacitance at said gate of said output PMOS device charges relatively slowly through said resistor, causing said output PMOS device to turn on relatively slowly; and whereby, when said enable signal closes said switch and said input signal turns said input NMOS device off, said intrinsic capacitance at said gate of said output NMOS device charges relatively slowly through said resistor, causing said output NMOS device to turn on relatively slowly.
Claim 5
Dependent Claim
33 words
The CMOS 3-state driver of claim 1, wherein said resistor is a resistive circuit element selected from the group consisting of a polysilicon resistor, a P+ diffusion resistor, and an N+ diffusion resistor.
Claim 6
Dependent Claim
34 words
The CMOS 3-state driver of claim 1, wherein said enabling means includes a PMOS device and an NMOS device coupled in parallel between said resistor and said gate of one of said output devices.
Claim 7
Dependent Claim
246 words
An integrated circuit CMOS 3-state driver, comprising: an input port which receives an input signal, an enable port which receives an enable signal, and an output port which provides an output signal; a CMOS output stage, including an output PMOS device and an output NMOS device coupled in series between first and second power sources, said PMOS and NMOS output devices each including a gate and a drain coupled to said output port; a CMOS input stage coupled to said CMOS output stage, said CMOS input stage including a second PMOS device, a resistor, a switch, and a second NMOS device coupled in series between first and second power sources; said resistor having resistance at least five times as large as said second PMOS device's on-channel resistance; said second PMOS and second NMOS devices each including a gate coupled to said input port; said second PMOS device having a drain coupled to said gate of said output PMOS device; said second NMOS device having a drain coupled to said gate of said output NMOS device; and said switch being coupled to said enable port, wherein said enable signal opens and closes said switch; wherein said resistor forms an RC delay circuit in conjunction with intrinsic capacitance present at said gates of said PMOS and NMOS output devices; whereby said output signal at said output port has increased transition times and reduced harmonic content compared to an output signal generated by a CMOS driver without said resistor.
Claim 8
Dependent Claim
246 words
An integrated circuit CMOS 3-state driver, comprising: an input port which receives an input signal, an enable port which receives an enable signal, and an output port which provides an output signal; a CMOS output stage, including an output PMOS device and an output NMOS device coupled in series between first and second power sources, said PMOS and NMOS output devices each including a gate and a drain coupled to said output port; a CMOS input stage coupled to said CMOS output stage, said CMOS input stage including a second PMOS device, a resistor, a switch, and a second NMOS device coupled in series between first and second power sources; said resistor having resistance at least five times as large as said second PMOS device's on-channel resistance; said second PMOS and second NMOS devices each including a gate coupled to said input port; said second PMOS device having a drain coupled to said gate of said output PMOS device; said second NMOS device having a drain coupled to said gate of said output NMOS device; and said switch being coupled to said enable port, wherein said enable signal opens and closes said switch; wherein said resistor forms an RC delay circuit in conjunction with intrinsic capacitance present at said gates of said PMOS and NMOS output devices; whereby said output signal at said output port has increased transition times and reduced harmonic content compared to an output signal generated by a CMOS driver without said resistor.
Claim 9
Dependent Claim
19 words
The CMOS 3-state driver of claim 5, wherein said resistor has a resistance between 1 KΩ and 10 KΩ.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1995-06-09 | 1995-12-09 | 1996-06-09 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1999-06-09 | 1999-12-09 | 2000-06-09 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2003-06-09 | 2003-12-09 | 2004-06-09 | $7700.00 | Window Closed / Lapsed |