Semiconductor device

Claim 2

A product produced by the process of: providing a gate insulative layer on a semiconductor wafer substrate; providing a first layer of a first material over the gate insulative layer, the first material being electrically conductive or capable of being rendered electrically conductive; etching the first layer and gate layer to expose a contact area; providing a second layer of second material over the contact area and first layer, the second material being selectively etchable relative to the first material and the substrate; etching the second layer selectively relative to the first material and the substrate to provide a pair of buried contact spacers over respective opposing edges of the first layer in the contact area, and to reexpose a portion of the contact area and the first layer; providing a third layer of a third material over the first layer, the buried contact spacers and the exposed portion of the contact area, the third material being electrically conductive or capable of being rendered electrically conductive; etching the first and third layers to define a transistor gate of one device and a transistor gate of another device, and to interconnect the transistor gate of the another device to the portion of the contact area with the third layer material, and to define an exposed region adjacent both the one gate and one of the buried contact spacers; providing insulative spacers about edges of the transistor gates; providing a conductivity enhancing impurity implant into the substrate through the exposed region; rendering the portion of the contact area within the substrate electrically conductive; and rendering substrate beneath the one buried contact spacer electrically conductive to electrically interconnect the portion of the contact area within the substrate to the conductivity enhancing impurity implanted region of the substrate.

Claim 3

A product produced by the process of: providing a gate insulative layer on a semiconductor wafer substrate; providing a first layer of a first material over the gate insulative layer, the first material being electrically conductive or capable of being rendered electrically conductive; etching the first layer and gate layer to expose a contact area; depositing a second layer of second material over the contact area and first layer, the second material being selectively etchable relative to the first material and the substrate, the second material being in situ doped with a semiconductor conductivity enhancing material during the depositing of the second layer; etching the second layer selectively relative to the first material and the substrate to provide a pair of buried contact spacers over respective opposing edges of the first layer in the contact area, and to reexpose a portion of the contact area and the first layer; providing a third layer of a third material over the first layer, the buried contact spacers and the exposed portion of the contact area, the third material being electrically conductive or capable of being rendered electrically conductive; etching the first and third layers to define a transistor gate of one device and a transistor gate of another device, and to interconnect the transistor gate of the another device to the portion of the contact area with the third layer material, and to define an exposed region adjacent both the one gate and one of the buried contact spacers; providing insulative spacers about edges of the transistor gates; providing a conductivity enhancing impurity implant into the substrate through the exposed region; rendering the portion of the contact area within the substrate electrically conductive; and diffusing conductivity enhancing material from the one buried contact spacer into substrate area immediately therebelow to render such substrate area electrically conductive and to electrically interconnect the portion of the contact area within the substrate to the conductivity enhancing impurity implanted region of the substrate.

Claim 4

A product produced by the process of: providing a gate insulative layer on a semiconductor wafer substrate; providing a first layer of a first material over the gate insulative layer, the first material being electrically conductive or capable of being rendered electrically conductive; etching the first layer and gate layer to expose a contact area; depositing a second layer of second material over the contact area and first layer, the second material being selectively etchable relative to the first material and the substrate, the second material being in situ doped with a semiconductor conductivity enhancing material during the depositing of the second layer; etching the second layer selectively relative to the first material and the substrate to provide a pair of buried contact spacers over respective opposing edges of the first layer in the contact area, and to reexpose a portion of the contact area and the first layer; providing a third layer of a third material over the first layer, the buried contact spacers and the exposed portion of the contact area, the third material being electrically conductive or capable of being rendered electrically conductive; etching the first and third layers to define a transistor gate of one device and a transistor gate of another device, and to interconnect the transistor gate of the another device to the portion of the contact area with the third layer material, and to define an exposed region adjacent both the one gate and one of the buried contact spacers; providing insulative spacers about edges of the transistor gates; providing a conductivity enhancing impurity implant into the substrate through the exposed region; rendering the portion of the contact area within the substrate electrically conductive; and diffusing conductivity enhancing material from the one buried contact spacer into substrate area immediately therebelow to render such substrate area electrically conductive and to electrically interconnect the portion of the contact area within the substrate to the conductivity enhancing impurity implanted region of the substrate.

Claim 5

A product produced by the process of: providing a gate insulative layer on a semiconductor wafer substrate; providing a first layer of a first material over the gate insulative layer, the first material being electrically conductive or capable of being rendered electrically conductive; etching the first layer and gate layer to expose a contact area; providing a conductivity enhancing impurity into the substrate contact area; providing a second layer of second material over the contact area and first layer, the second material being selectively etchable relative to the first material and the substrate; after providing the conductivity enhancing impurity into the substrate contact area, etching the second layer selectively relative to the first material and the substrate to provide a pair of buried contact spacers over respective opposing edges of the first layer in the contact area, and to reexpose a portion of the contact area and the first layer, the substrate area beneath one of the buried contact spacers being electrically conductive as a result of the previous conductivity enhancing impurity being provided into the whole of the substrate contact area; providing a third layer of a third material over the first layer, the buried contact spacers and the exposed portion of the contact area, the third material being electrically conductive or capable of being rendered electrically conductive; etching the first and third layers to define a transistor gate of one device and a transistor gate of another device, and to interconnect the transistor gate of the another device to the portion of the contact area with the third layer material, and to define an exposed region adjacent both the one gate and the one buried contact spacer; providing insulative spacers about edges of the transistor gates; and providing a conductivity enhancing impurity implant into the substrate through the exposed region.

Claim 6

A product produced by the process of: providing a gate insulative layer on a semiconductor wafer substrate; providing a first layer of a first material over the gate insulative layer, the first material being electrically conductive or capable of being rendered electrically conductive; etching the first layer and gate layer to expose a contact area; providing a conductivity enhancing impurity into the substrate contact area; providing a second layer of second material over the contact area and first layer, the second material being selectively etchable relative to the first material and the substrate; after providing the conductivity enhancing impurity into the substrate contact area, etching the second layer selectively relative to the first material and the substrate to provide a pair of buried contact spacers over respective opposing edges of the first layer in the contact area, and to reexpose a portion of the contact area and the first layer, the substrate area beneath one of the buried contact spacers being electrically conductive as a result of the previous conductivity enhancing impurity being provided into the whole of the substrate contact area; providing a third layer of a third material over the first layer, the buried contact spacers and the exposed portion of the contact area, the third material being electrically conductive or capable of being rendered electrically conductive; etching the first and third layers to define a transistor gate of one device and a transistor gate of another device, and to interconnect the transistor gate of the another device to the portion of the contact area with the third layer material, and to define an exposed region adjacent both the one gate and the one buried contact spacer; providing insulative spacers about edges of the transistor gates; and providing a conductivity enhancing impurity implant into the substrate through the exposed region.

Claim 7

A semiconductor device formed within a semiconductor substrate comprising: a pair of first and second field effect transistors having respective gates and active areas; one of the active areas of the first transistor having an overlying buried contact spacer, the buried contact spacer covering only a portion of the one active area and predominately comprising an oxide material; and an electrical interconnect extending from the gate of the second transistor to the one active area, the electrical interconnect overlapping the buried contact spacer.

Claim 8

A semiconductor device formed within a semiconductor substrate comprising: a pair of first and second field effect transistors having respective gates and active areas; one of the active areas of the first transistor having an overlying buried contact spacer, the buried contact spacer covering only a portion of the one active area and predominately comprising an oxide material; and an electrical interconnect extending from the gate of the second transistor to the one active area, the electrical interconnect overlapping the buried contact spacer.

Claim 9

A semiconductor device formed within a semiconductor substrate comprising: a pair of first and second field effect transistors having respective gates and active areas; one of the active areas of the first transistor having an overlying buried contact spacer, the buried contact spacer covering only a portion of the one active area and predominately comprising an oxide material; and an electrical interconnect extending from the gate of the second transistor to the one active area, the electrical interconnect overlapping the buried contact spacer, the electrical interconnect having a terminating edge, the terminating edge being positioned over the buried contact spacer.

Claim 10

A semiconductor device formed within a semiconductor substrate comprising: a pair of first and second field effect transistors having respective gates and active areas; one of the active areas of the first transistor having an overlying buried contact spacer, the buried contact spacer covering only a portion of the one active area and predominately comprising an oxide material; and an electrical interconnect extending from the gate of the second transistor to the one active area, the electrical interconnect overlapping the buried contact spacer, the electrical interconnect having a terminating edge, the terminating edge being positioned over the buried contact spacer.

Claim 11

A semiconductor device formed within a semiconductor substrate comprising: a pair of first and second field effect transistors having respective gates and active areas; one of the active areas of the first transistor having an overlying buried contact spacer, the buried contact spacer being comprised predominately of an insulating material, the buried contact spacer covering only a portion of the one active area; and an electrical interconnect extending from the gate of the second transistor to the one active area, the electrical interconnect overlapping the buried contact spacer.

Claim 12

A semiconductor device formed within a semiconductor substrate comprising: a pair of first and second field effect transistors having respective gates and active areas; one of the active areas of the first transistor having an overlying buried contact spacer, the buried contact spacer being comprised predominately of an insulating material, the buried contact spacer covering only a portion of the one active area; and an electrical interconnect extending from the gate of the second transistor to the one active area, the electrical interconnect overlapping the buried contact spacer.

Claim 13

The semiconductor device of claim 6 wherein the electrical interconnect has a terminating edge, the terminating edge being positioned over the buried contact spacer.