Patent US5315241A successfully refreshed from Google Patents.
US5315241A
Expired / Lapsed
US
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Method for testing integrated circuits
Assignee: STMicroelectronics lnc USA
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Filing: 1991-09-18
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Granted: 1994-05-24
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Expires: 2011-09-18
Abstract
Abstract A substrate is provided as a test fixture for burning-in and testing integrated circuit devices. The substrate contains a plurality of unpackaged integrated circuit dice arranged in a regular matrix of rows and columns. The substrate is partitioned into an array of rectangles which can be easily broken apart. One integrated circuit die is attached in each rectangle. The integrated circuits are bonded to conductive traces in their respective rectangular areas, and the conductive traces are connected to common locations at one side of the substrate. Voltages can be applied to all of the devices simultaneously by contacting the common locations at the edge of the substrate. This allows for burn-in of all integrated circuit devices on the substrate in parallel, after which they can be separated and used individually on printed circuit boards.
Inventors
- 👤 Charles R. Ewers
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-03 15:24
CPC Classifications
G; G01; G01R; G01R31/00; G01R31/28; G01R31/2851; G01R31/2886
Claims Analysis
Total Claims: 24
Claim 1
Independent Claim
180 words
A method for testing integrated circuit devices, comprising the steps of: attaching a plurality of integrated circuit dice, containing a desired plurality of devices, to an insulating substrate having conductive traces on an upper surface and a lower surface thereof, wherein said insulating substrate is divided into a plurality of regions defined by multiple lines of conductive through holes therethrough, and wherein said conductive traces on said upper surface are electrically connected to said conductive traces on said lower surface through said through holes; wire bonding to connect bonding wires from conductive bond pads on said integrated circuit dice to corresponding bonding locations on said traces on said upper surface; providing electrical power and signals to said integrated circuit dice through said conductive traces on said lower surface, wherein the signals are connected to said integrated circuit dice through said through holes, said conductive traces on said upper surface, and said bonding wires, for at least a predetermined burn-in period; physically breaking said conductive traces to at least partially isolate said integrated circuit dice; and testing said integrated circuit dice.
Claim 2
Independent Claim
180 words
A method for testing integrated circuit devices, comprising the steps of: attaching a plurality of integrated circuit dice, containing a desired plurality of devices, to an insulating substrate having conductive traces on an upper surface and a lower surface thereof, wherein said insulating substrate is divided into a plurality of regions defined by multiple lines of conductive through holes therethrough, and wherein said conductive traces on said upper surface are electrically connected to said conductive traces on said lower surface through said through holes; wire bonding to connect bonding wires from conductive bond pads on said integrated circuit dice to corresponding bonding locations on said traces on said upper surface; providing electrical power and signals to said integrated circuit dice through said conductive traces on said lower surface, wherein the signals are connected to said integrated circuit dice through said through holes, said conductive traces on said upper surface, and said bonding wires, for at least a predetermined burn-in period; physically breaking said conductive traces to at least partially isolate said integrated circuit dice; and testing said integrated circuit dice.
Claim 3
Dependent Claim
25 words
The method of claim 1, further comprising the steps of: before said electrical power providing step, applying a protective covering over the integrated circuit dice.
Claim 4
Dependent Claim
41 words
The method of claim 1, further comprising the steps of: after said testing step, breaking the substrate along the linear series of through holes separating the substrate regions to provide a plurality of secondary substrates each containing one integrated circuit die.
Claim 5
Dependent Claim
13 words
The method of claim 1, wherein said insulating substrate consists essentially of alumina.
Claim 6
Dependent Claim
11 words
The method of claim 1, wherein said attaching step uses epoxy.
Claim 7
Independent Claim
115 words
A method of testing integrated circuits, comprising the steps of: affixing individual integrated circuits to respective portions of a breakable insulating substrate having conductive traces thereon; wire-bonding electrical contact pads of each of said integrated circuits to respective ones of said traces; burning-in said integrated circuits while supplying power through said traces; physically severing at least some ones of said traces, to at least partially isolate said integrated circuits; electrically testing said integrated circuits; breaking apart said insulating substrate, to sever said traces and provide multiple fragments having respective ones of said integrated circuits thereon; and packaging at least some ones of said integrated circuits with respective fragments of said insulating substrate still adhered thereto.
Claim 8
Independent Claim
115 words
A method of testing integrated circuits, comprising the steps of: affixing individual integrated circuits to respective portions of a breakable insulating substrate having conductive traces thereon; wire-bonding electrical contact pads of each of said integrated circuits to respective ones of said traces; burning-in said integrated circuits while supplying power through said traces; physically severing at least some ones of said traces, to at least partially isolate said integrated circuits; electrically testing said integrated circuits; breaking apart said insulating substrate, to sever said traces and provide multiple fragments having respective ones of said integrated circuits thereon; and packaging at least some ones of said integrated circuits with respective fragments of said insulating substrate still adhered thereto.
Claim 9
Dependent Claim
13 words
The method of claim 6, wherein said insulating substrate consists essentially of alumina.
Claim 10
Dependent Claim
11 words
The method of claim 6, wherein said affixing step uses epoxy.
Claim 11
Dependent Claim
24 words
The method of claim 6, further comprising the additional step of encapsulating said integrated circuit on said substrate, after said step of electrically testing.
Claim 12
Dependent Claim
22 words
The method of claim 6, further comprising the subsequent step of affixing said fragments of said substrate to a respective primary substrate.
Claim 13
Independent Claim
125 words
A method of testing integrated circuits, comprising the steps of: affixing individual integrated circuits to respective portions of a breakable insulating substrate having conductive traces thereon, and conductive through-holes positioned to define breakage lines; wire-bonding electrical contact pads of each said integrated circuit to respective ones of said traces; burning-in said integrated circuits while supplying power through said traces; physically severing at least some ones of said traces, to at least partially isolate said integrated circuits; electrically testing said integrated circuits; breaking apart said insulating substrate, to sever said traces and provide multiple fragments having respective ones of said integrated circuits thereon; and forming electrical connections to said through-holes of said fragments, to thereby form electrical connections to said contact pads of said integrated circuits.
Claim 14
Independent Claim
125 words
A method of testing integrated circuits, comprising the steps of: affixing individual integrated circuits to respective portions of a breakable insulating substrate having conductive traces thereon, and conductive through-holes positioned to define breakage lines; wire-bonding electrical contact pads of each said integrated circuit to respective ones of said traces; burning-in said integrated circuits while supplying power through said traces; physically severing at least some ones of said traces, to at least partially isolate said integrated circuits; electrically testing said integrated circuits; breaking apart said insulating substrate, to sever said traces and provide multiple fragments having respective ones of said integrated circuits thereon; and forming electrical connections to said through-holes of said fragments, to thereby form electrical connections to said contact pads of said integrated circuits.
Claim 15
Dependent Claim
13 words
The method of claim 11, wherein said insulating substrate consists essentially of alumina.
Claim 16
Dependent Claim
11 words
The method of claim 11, wherein said affixing step uses epoxy.
Claim 17
Dependent Claim
24 words
The method of claim 11, further comprising the additional step of encapsulating said integrated circuit on said substrate, after said step of electrically testing.
Claim 18
Dependent Claim
30 words
The method of claim 11, further comprising the additional step, prior to said step of forming electrical connections, of affixing said fragments of said substrate to a respective primary substrate.
Claim 19
Independent Claim
134 words
A method of testing integrated circuits, comprising the steps of: affixing individual integrated circuits to respective portions of a breakable insulating substrate having conductive traces thereon, and conductive through-holes positioned to define breakage lines; wire-bonding electrical contact pads of each said integrated circuit to respective ones of said traces; burning-in said integrated circuits while supplying power through said traces; breaking off an edge portion of said substrate to physically sever at least some ones of said traces, to at least partially isolate said integrated circuits; electrically testing said integrated circuits; breaking apart said insulating substrate, to sever said traces and provide multiple fragments having respective ones of said integrated circuits thereon; and forming electrical connections to said through-holes of said fragments, to thereby form electrical connections to said contact pads of said integrated circuits.
Claim 20
Independent Claim
134 words
A method of testing integrated circuits, comprising the steps of: affixing individual integrated circuits to respective portions of a breakable insulating substrate having conductive traces thereon, and conductive through-holes positioned to define breakage lines; wire-bonding electrical contact pads of each said integrated circuit to respective ones of said traces; burning-in said integrated circuits while supplying power through said traces; breaking off an edge portion of said substrate to physically sever at least some ones of said traces, to at least partially isolate said integrated circuits; electrically testing said integrated circuits; breaking apart said insulating substrate, to sever said traces and provide multiple fragments having respective ones of said integrated circuits thereon; and forming electrical connections to said through-holes of said fragments, to thereby form electrical connections to said contact pads of said integrated circuits.
Claim 21
Dependent Claim
13 words
The method of claim 16, wherein said insulating substrate consists essentially of alumina.
Claim 22
Dependent Claim
11 words
The method of claim 16, wherein said affixing step uses epoxy.
Claim 23
Dependent Claim
24 words
The method of claim 16, further comprising the additional step of encapsulating said integrated circuit on said substrate, after said step of electrically testing.
Claim 24
Dependent Claim
30 words
The method of claim 16, further comprising the additional step, prior to said step of forming electrical connections, of affixing said fragments of said substrate to a respective primary substrate.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1997-05-23 | 1997-11-22 | 1998-05-24 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-05-23 | 2001-11-22 | 2002-05-24 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-05-23 | 2005-11-22 | 2006-05-24 | $7700.00 | Window Closed / Lapsed |