Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
349 words
A circuit for synchronously selecting either a first or second input clock signal as an output clock signal in response to an asynchronously generated select signal, said circuit comprising: first and second flip-flops coupled in series and clocked by said first clock signal, the data input of said flip-flop being coupled to a first internal control signal; third and fourth flip-flops coupled in series and clocked by said second clock signal, the data input of said third flip-flop being coupled to said first internal clock signal; fifth and sixth flip-flops coupled in series and clocked by said output clock signal, the data input of said fifth flip-flop being coupled to receive said select signal, said sixth flip-flop generating said first internal control signal and a second internal control signal; a first logic gate for gating said first clock signal with an output of said second flip-flop, and a second logic gate for gating said second clock signal with an output of said fourth flip-flop; a logic network comprising third, fourth, and fifth logic gates, said third logic gate having first and second inputs coupled to an output of said first logic gate and said first control signal, said fourth logic gate having first and second inputs coupled to an output of said second logic gate and said second control signal, said fifth logic gate having first and second inputs coupled to outputs of said third and fourth logic gates, an output of said fifth logic gate generating said output clock signal; said logic network selecting either said first or said second clock signal as said output signal in response to said first and second internal control signals, wherein when said select signal transitions from a first logic level to a second logic level, said first and second internal control signals synchronously switch logic state, thereby causing said logic network to hold said output clock signal for a predetermined time before synchronously selecting said second clock signal as said output clock signal, the switching of said output clock signal from said first to said second clock signal occurring without glitching.
Claim 2
Dependent Claim
349 words
A circuit for synchronously selecting either a first or second input clock signal as an output clock signal in response to an asynchronously generated select signal, said circuit comprising: first and second flip-flops coupled in series and clocked by said first clock signal, the data input of said flip-flop being coupled to a first internal control signal; third and fourth flip-flops coupled in series and clocked by said second clock signal, the data input of said third flip-flop being coupled to said first internal clock signal; fifth and sixth flip-flops coupled in series and clocked by said output clock signal, the data input of said fifth flip-flop being coupled to receive said select signal, said sixth flip-flop generating said first internal control signal and a second internal control signal; a first logic gate for gating said first clock signal with an output of said second flip-flop, and a second logic gate for gating said second clock signal with an output of said fourth flip-flop; a logic network comprising third, fourth, and fifth logic gates, said third logic gate having first and second inputs coupled to an output of said first logic gate and said first control signal, said fourth logic gate having first and second inputs coupled to an output of said second logic gate and said second control signal, said fifth logic gate having first and second inputs coupled to outputs of said third and fourth logic gates, an output of said fifth logic gate generating said output clock signal; said logic network selecting either said first or said second clock signal as said output signal in response to said first and second internal control signals, wherein when said select signal transitions from a first logic level to a second logic level, said first and second internal control signals synchronously switch logic state, thereby causing said logic network to hold said output clock signal for a predetermined time before synchronously selecting said second clock signal as said output clock signal, the switching of said output clock signal from said first to said second clock signal occurring without glitching.
Claim 3
Dependent Claim
19 words
The circuit of claim 1 wherein said first and second input clock signals have different frequencies and/or phase relationships.
Claim 4
Dependent Claim
28 words
The circuit of claim 2 wherein said first input clock signal is selected as said output clock signal when said select signal is at a logical high level.