Semiconductor memory device having a double-stacked capacitor structure

Claim 1

A semiconductor memory device having a double-stacked capacitor structure, comprising: MOSFETs each with a gate electrode, a source electrode and a drain electrode formed on a substrate; a first charge storage electrode in contact with a source electrode of said MOSFETs through a first contact hole, and extended over a part of said gate electrode, with an insulating layer between said first charge storage electrode and the MOSFETs; a first of two stacked capacitors, said first capacitor having a first dielectric layer and a first plate electrode sequentially formed over said first charge storage electrode; a second and third insulating layer sequentially formed over said first plate electrode, with a bit line formed between said second insulating layer and said third insulating layer, said bit line being in contact with a drain electrode of said MOSFETs through a second contact hole; a third contact hole formed over said first charge storage electrode by removing a part of said second and third insulating layer, of said first plate electrode, and of said first dielectric layer; a second charge storage electrode formed over said third insulating layer and in contact with said first charge storage electrode through said third contact hole; and a second stacked capacitor having a second dielectric layer and a second plate electrode sequentially formed over said second charge storage electrode, whereby a first and a second capacitor connected are formed in parallel respectively below and over said bit line.