Patent US5313172A successfully refreshed from Google Patents.
US5313172A
Expired / Lapsed
US
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Digitally switched gain amplifier for digitally controlled automatic gain control amplifier applications
Assignee: Boeing North American Inc
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Filing: 1992-12-11
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Granted: 1994-05-17
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Expires: 2012-12-11
Abstract
Abstract A digitally switched gain amplifier designed for use in binary controlled systems. The amplifier is designed for fabrication as a monolithic integrated circuit. The amplifier provides gain that varies in discrete levels in a binary manner under direct control of a digital word. The smallest resolution, or distance between gain steps, is one decibel and the maximum amount of gain reduction is determined by the number of stages included in the amplifier. The incremental resolution of the amplifier allows for the amplifier to keep a received signal at a constant level with a digital word. Thus, eliminating the need for digital to analog conversion.
Inventors
- 👤 Michael R. Vagher
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-07 15:24
CPC Classifications
H; H03; H03G; H03G3/00; H03G3/001
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
97 words
A digitally switched gain amplifier designed for use in binary controlled systems comprising: a plurality of amplifier gain cells serially coupled to each other, said amplifier gain cells comprising paired transistors and paired emitter resistors and load resistors and of alternating gain of four states and two states, respectively; and control circuitry coupled to each amplifier gain cell said contol circuitry including switching means responsive to a first control signal for enabling the amplifier cells in predetermined configurations, where the gain is provided approximately by the ration of the active emitter resistor to the active load resistor.
Claim 2
Dependent Claim
97 words
A digitally switched gain amplifier designed for use in binary controlled systems comprising: a plurality of amplifier gain cells serially coupled to each other, said amplifier gain cells comprising paired transistors and paired emitter resistors and load resistors and of alternating gain of four states and two states, respectively; and control circuitry coupled to each amplifier gain cell said contol circuitry including switching means responsive to a first control signal for enabling the amplifier cells in predetermined configurations, where the gain is provided approximately by the ration of the active emitter resistor to the active load resistor.
Claim 3
Dependent Claim
16 words
The apparatus of claim 1, wherein the gain amplifier is comprised of five amplifier gain cells.
Claim 4
Dependent Claim
15 words
The apparatus of claim 1, wherein the smallest distance between gain steps is one decibel.
Claim 5
Dependent Claim
109 words
A digitally switched gain amplifier designed for use in binary controlled systems and implemented in a monolithic integrated circuit comprising: a plurality of amplifier gain cells serially coupled to each other, of alternating gain of four states and two states, respectively, each two state amplifier gain cell comprised of four transistors, each four state amplifier gain cell comprised of eight transistors; and control circuitry coupled to each amplifier gain cell said control circuitry including switching means responsive to a first control signal for enabling the amplifier cells in predetermined configurations, where the gain is provided approximately by the ratio of the active emitter resistor to the active load resistor.
Claim 6
Dependent Claim
109 words
A digitally switched gain amplifier designed for use in binary controlled systems and implemented in a monolithic integrated circuit comprising: a plurality of amplifier gain cells serially coupled to each other, of alternating gain of four states and two states, respectively, each two state amplifier gain cell comprised of four transistors, each four state amplifier gain cell comprised of eight transistors; and control circuitry coupled to each amplifier gain cell said control circuitry including switching means responsive to a first control signal for enabling the amplifier cells in predetermined configurations, where the gain is provided approximately by the ratio of the active emitter resistor to the active load resistor.
Claim 7
Dependent Claim
15 words
The apparatus of claim 4, wherein the smallest distance between gain steps is one decibel.
Claim 8
Dependent Claim
16 words
The apparatus of claim 4, wherein the transistors are of the type known as NPN transistors.
Claim 9
Dependent Claim
16 words
The apparatus of claim 4, wherein the gain amplifier is comprised of five amplifier gain cells.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1997-05-16 | 1997-11-15 | 1998-05-17 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-05-16 | 2001-11-15 | 2002-05-17 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-05-16 | 2005-11-15 | 2006-05-17 | $7700.00 | Window Closed / Lapsed |