Patent US5311469A successfully refreshed from Google Patents.
US5311469A
Expired / Lapsed
US
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Semiconductor memory device
Assignee: Toshiba Corp
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Filing: 1992-03-04
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Granted: 1994-05-10
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Expires: 2012-03-04
Abstract
Abstract A semiconductor memory device including: a memory cell array having at least one cell array unit, the cell array unit including a plurality of memory cells; a decoder for selecting at least one the memory cell in accordance with an externally supplied address; an input/output terminal for outputting data read from the selected memory cell and for receiving data supplied externally and sending the data to the selected memory cell; at least one data line for connecting the input/output terminal to each the cell array unit; sense amplifiers serially connected to each the data line in a multiple stage configuration for amplifying the read data; a write buffer connected in parallel with one of the sense amplifiers connected to each data line; by-pass switching elements connected between input and output terminals of the other sense amplifiers connected to each the data line; and a control circuit for applying an on-signal to at least one by-pass switching element when writing data, the on-signal turning on at least one by-pass switching element.
Inventors
- 👤 Satoru Hoshi
- 👤 Masami Masuda
- 👤 Kazuhiko Takahashi
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 14:49
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C7/00; G11C7/06; G11C7/10; G11C7/1048; G11C7/1051
Claims Analysis
Total Claims: 16
Claim 1
Independent Claim
191 words
A semiconductor memory device comprising: a memory cell array having at least one cell array unit, said cell array unit including a plurality of memory cells; selection means for selecting at least one of said memory cells in accordance with an externally supplied address; an input/output terminal for outputting data read form said selected memory cell and for receiving data supplied externally and sending said data to said selected memory cell; at least one data line for connecting said input/output terminal to each said cell array unit; sense amplifiers serially connected to each said data line in a multiple stage configuration for amplifying said read data; a write buffer connected in parallel with one of said sense amplifiers connected to each said data line; by-pass switching means connected between input and output terminals of the other sense amplifiers connected to each said data line; a control circuit for applying an on-signal to at least one said by-pass switching means when writing data, said ion-signal turning on said by-pass switching means; and a read/write selector, said control circuit receiving a write mode signal outputted from said read/write selector and outputting said on-signal.
Claim 2
Dependent Claim
191 words
A semiconductor memory device comprising: a memory cell array having at least one cell array unit, said cell array unit including a plurality of memory cells; selection means for selecting at least one of said memory cells in accordance with an externally supplied address; an input/output terminal for outputting data read form said selected memory cell and for receiving data supplied externally and sending said data to said selected memory cell; at least one data line for connecting said input/output terminal to each said cell array unit; sense amplifiers serially connected to each said data line in a multiple stage configuration for amplifying said read data; a write buffer connected in parallel with one of said sense amplifiers connected to each said data line; by-pass switching means connected between input and output terminals of the other sense amplifiers connected to each said data line; a control circuit for applying an on-signal to at least one said by-pass switching means when writing data, said ion-signal turning on said by-pass switching means; and a read/write selector, said control circuit receiving a write mode signal outputted from said read/write selector and outputting said on-signal.
Claim 3
Dependent Claim
39 words
A semiconductor memory device according to claim 1, wherein said control circuit receives a read mode signal outputted from said selector and outputs said on-signal, said by-pass switching means also functioning as input/output terminal equalizing means for data reading.
Claim 4
Dependent Claim
95 words
A semiconductor memory device according to claim 1, wherein each said sense amplifier further comprises input side complementary data lines equalizing switching means connected between said complementary data lines on the input side of said sense amplifier, and output side complementary data lines equalizing switching means connected between said complementary data lines on the output side of said sense amplifier, and wherein said control circuit receives said read mode signal outputted from said selector and outputs input side/output side on-signals for turning on said input side and output side complementary data lines equalizing switching means.
Claim 5
Dependent Claim
95 words
A semiconductor memory device according to claim 2, wherein each said sense amplifier further comprises input side complementary data lines equalizing switching means connected between said complementary data lines on the input side of said sense amplifier, and output side complementary data lines equalizing switching means connected between said complementary data lines on the output side of said sense amplifier, and wherein said control circuit receives said read mode signal outputted from said selector and outputs input side/output side on-signals for turning on said input side and output side complementary data lines equalizing switching means.
Claim 6
Dependent Claim
233 words
A semiconductor memory device comprising: a memory cell array having at least one cell array unit, said cell array unit including a plurality of memory cells; selection means for selecting at least one of said memory cells in accordance with an externally supplied address; an input/output terminal for outputting data read from said selected memory cell and for receiving data supplied externally and sending said data to said selected memory cell; at least one data line for connecting said input/output terminal to each said cell array unit; sense amplifiers serially connected to each said data line in a multiple stage configuration for amplifying said read data; a write buffer connected in parallel with one of said sense amplifiers connected to each said data line; by-pass switching means connected between input and output terminals of the other sense amplifiers connected to each said data line; a control circuit for applying an on-signal to at least one said by-pass switching means when writing data, said on-signal turning on said by-pass switching means; and a read/write selector, said control circuit receiving a write mode signal outputted from said read/write selector and outputting said on/signal, wherein said data line is a pair of complementary data lines for transferring complementary data to and from each said memory cell, and wherein said selection means includes a row decoder and a column decoder, respectively for receiving and decoding an address.
Claim 7
Dependent Claim
233 words
A semiconductor memory device comprising: a memory cell array having at least one cell array unit, said cell array unit including a plurality of memory cells; selection means for selecting at least one of said memory cells in accordance with an externally supplied address; an input/output terminal for outputting data read from said selected memory cell and for receiving data supplied externally and sending said data to said selected memory cell; at least one data line for connecting said input/output terminal to each said cell array unit; sense amplifiers serially connected to each said data line in a multiple stage configuration for amplifying said read data; a write buffer connected in parallel with one of said sense amplifiers connected to each said data line; by-pass switching means connected between input and output terminals of the other sense amplifiers connected to each said data line; a control circuit for applying an on-signal to at least one said by-pass switching means when writing data, said on-signal turning on said by-pass switching means; and a read/write selector, said control circuit receiving a write mode signal outputted from said read/write selector and outputting said on/signal, wherein said data line is a pair of complementary data lines for transferring complementary data to and from each said memory cell, and wherein said selection means includes a row decoder and a column decoder, respectively for receiving and decoding an address.
Claim 8
Dependent Claim
39 words
A semiconductor memory device according to claim 5, wherein said control circuit receives a read mode signal outputted from said selector and outputs said on-signal, said by-pass switching means also functioning as input/output terminal equalizing means for data reading.
Claim 9
Dependent Claim
95 words
A semiconductor memory device according to claim 5, wherein each said sense amplifier further comprises input side complementary data lines equalizing switching means connected between said complementary data lines on the input side of said sense amplifier, and output side complementary data lines equalizing switching means connected between said complementary data lines on the output side of said sense amplifier, and wherein said control circuit receives said read mode signal outputted from said selector and outputs input side/output side on-signals for turning on said input side and output side complementary data lines equalizing switching means.
Claim 10
Dependent Claim
95 words
A semiconductor memory device according to claim 6, wherein each said sense amplifier further comprises input side complementary data lines equalizing switching means connected between said complementary data lines on the input side of said sense amplifier, and output side complementary data lines equalizing switching means connected between said complementary data lines on the output side of said sense amplifier, and wherein said control circuit receives said read mode signal outputted form said selector and outputs input side/output side on-signals for turning on said input side and output side complementary data lines equalizing switching means.
Claim 11
Dependent Claim
208 words
A semiconductor memory device comprising: a memory cell array having cell array units, said cell array units including a plurality of memory cells; selection means for selecting at least one of said memory cells in accordance with an externally supplied address, said selection means includes a row decoder and a column decoder, respectively, for receiving an decoding an address; an input/output terminal for outputting data read from said selected memory cell and for receiving data supplied externally and sending said data to said selected memory cell; at least one data line for connecting said input/output terminal to each of said cell array units; sense amplifiers serially connected to each said data line in a multiple stage configuration for amplifying said read data; a write buffer connected in parallel with one of said sense amplifiers connected to each said data line; by-pass switching means connected between input and output terminals of the other sense amplifiers connected to each said data line; a control circuit for applying an on-signal to at least one said by-pass switching means when writing data, said on-signal turning on said by-pass switching means; and a read/write selector for outputting a write mode signal to said control circuit so that said control circuit outputs said on-signal.
Claim 12
Dependent Claim
208 words
A semiconductor memory device comprising: a memory cell array having cell array units, said cell array units including a plurality of memory cells; selection means for selecting at least one of said memory cells in accordance with an externally supplied address, said selection means includes a row decoder and a column decoder, respectively, for receiving an decoding an address; an input/output terminal for outputting data read from said selected memory cell and for receiving data supplied externally and sending said data to said selected memory cell; at least one data line for connecting said input/output terminal to each of said cell array units; sense amplifiers serially connected to each said data line in a multiple stage configuration for amplifying said read data; a write buffer connected in parallel with one of said sense amplifiers connected to each said data line; by-pass switching means connected between input and output terminals of the other sense amplifiers connected to each said data line; a control circuit for applying an on-signal to at least one said by-pass switching means when writing data, said on-signal turning on said by-pass switching means; and a read/write selector for outputting a write mode signal to said control circuit so that said control circuit outputs said on-signal.
Claim 13
Dependent Claim
39 words
A semiconductor memory device according to claim 9, wherein said control circuit receives a read mode signal outputted from said selector and outputs said on-signal, said by-pass switching means also functioning as input/output terminal equalizing means for data reading.
Claim 14
Dependent Claim
30 words
A semiconductor memory device according to claim 10, wherein said data line comprises a pair of complimentary data lines for transferring complementary data to and from each said memory cell.
Claim 15
Dependent Claim
96 words
A semiconductor memory device according to claim 1-0, wherein each said sense amplifier further comprises input side complementary data lines equalizing switching means connected between said complementary data lines on the input side of said sense amplifier, and output side complementary data lines equalizing switching means connected between said complementary data lines on the output side of said sense amplifier, and wherein said control circuit receives said read mode signal outputted from said selector and outputs input side/output side on-signals for turning on said input side and said output side complementary data lines equalizing switching means.
Claim 16
Dependent Claim
95 words
A semiconductor memory device according to claim 11, wherein each said sense amplifier further comprises input side complementary data lines equalizing switching means connected between said complementary data lines on the input side of said sense amplifier, and output side complementary data lines equalizing switching means connected between said complementary data lines on the output side of said sense amplifier, and wherein said control circuit receives said read mode signal outputted from said selector and outputs input side/output side on-signals for turning on said input side and output side complementary data lines equalizing switching means.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1997-05-09 | 1997-11-08 | 1998-05-10 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-05-09 | 2001-11-08 | 2002-05-10 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-05-09 | 2005-11-08 | 2006-05-10 | $7700.00 | Window Closed / Lapsed |