Random access memory with a serial register arranged for quick access of a second bit from an arbitrary address

Claim 1

A random access memory comprising: at least one memory array including a plurality of storage cells arrange din addressable rows and columns; a row address decoder; a column address decoder; a serial register including a plurality of stages having taps; a serial register address decoder for enabling readout of data bits from sequentially addressed taps of the serial register stages; a serial address counter for generating and applying a sequence of tap addresses to the serial register address decoder; an initial bit data line connecting to the memory array; an odd bit data lead connecting with taps of odd address stages of the serial register; an even bit data lead connecting with taps of even address stages of the serial register; an odd/even multiplexer responsive to data bits carried from the taps of the serial register on the odd and even bit data leads for producing a sequence of other data bits from the serial register on a serial data line; a first bit multiplexer having a first input connecting with the initial bit data line of the memory array for reading out a first data bit from a storage cell of an initially addressed column of the memory array and having a second input connecting with the serial data line for reading out the sequence of other data bits from addressed taps of the serial register; and an increment circuit for either passing the initial tap address to the serial address decoder for accessing a second data bit of the sequence by way of the serial data line from the serial register to the first bit multiplexer or passing an incremented initial tap address to the serial address decoder for accessing the second data bit of the sequence by way of the serial data line from the serial register to the first bit multiplexer.