Method of and arrangement for suppressing noise in a digital signal

Claim 3

A method of suppressing noise as claimed in claim 1, characterized in that said method further comprises the steps: determining whether said determined difference is in a predetermined tolerance range around said predetermined difference value; and replacing said second sample value with a mean value of said second sample value and said first sample value if said determined difference is in said predetermined tolerance range.

Claim 4

An arrangement for suppressing noise in a digital signal obtained by sampling an analog signal, said arrangement comprising: a multiplexer having a first input for receiving sample values, and an output; a delay element coupled to the output of said multiplexer for delaying each sample value by one sample clock, said delay element having an output coupled to a second input of said multiplexer; a subtractor having a first input coupled to the output of said delay element, and a second input for receiving the sample values applied to the first input of said multiplexer; a quantity former coupled to an output of said subtractor; and a comparator coupled to an output of said quantity former for comparing an output signal therefrom to a predetermined difference value, an output of said comparator being coupled to a control input of said multiplexer, whereby said multiplexer is switched to the first input thereof if the predetermined difference value is exceeded, and otherwise is switched to the second input thereof.

Claim 5

An arrangement for suppressing noise in a digital signal obtained by sampling an analog signal, said arrangement comprising: a multiplexer having a first input for receiving sample values, and an output; a delay element coupled to the output of said multiplexer for delaying each sample value by one sample clock, said delay element having an output coupled to a second input of said multiplexer; a subtractor having a first input coupled to the output of said delay element, and a second input for receiving the sample values applied to the first input of said multiplexer; a quantity former coupled to an output of said subtractor; and a comparator coupled to an output of said quantity former for comparing an output signal therefrom to a predetermined difference value, an output of said comparator being coupled to a control input of said multiplexer, whereby said multiplexer is switched to the first input thereof if the predetermined difference value is exceeded, and otherwise is switched to the second input thereof.

Claim 6

An arrangement as claimed in claim 3, characterized a in that said arrangement further comprises means for forming a mean value of the sample value applied to the first input of the multiplexer and an output signal of said delay element, said multiplexer further comprises a third input to which said mean value is applied, and said comparator further determines whether the output signal from said quantity former is within a predetermined tolerance range of said predetermined difference value, whereupon said comparator causes said multiplexer to switch to the third input thereof.

Claim 7

An arrangement for suppressing noise in a digital signal obtained by sampling an analog signal, said arrangement comprising: a first multiplier for multiplying sample values by a factor 1/(1-K), where K is a predetermined constant value; a multiplexer having a first input coupled to an output of said first multiplier, and an output; a first delay element coupled to the output of said multiplexer for delaying the sample values each time by one sample clock; a second multiplier coupled to an output of said first delay element for multiplying the delayed sample values by the factor K; an adder having a first input coupled to an output of said second multiplier, and an output coupled to a second input of said multiplexer; a second delay element having an input for also receiving the sample values applied to said first multiplier for delaying said sample values by one sample clock, and an output coupled to a second input of said adder; a subtractor having a first and a second input coupled to the input and the output of said second delay element; a quantity former coupled to an output of said subtractor; and a comparator for comparing an output signal of said quantity former to a predetermined difference value, an output of said comparator being coupled to a control input of said multiplexer, whereby said multiplexer is switched to the first input if said predetermined difference value is exceeded, and otherwise is switched to the second input.

Claim 8

An arrangement for suppressing noise in a digital signal obtained by sampling an analog signal, said arrangement comprising: a first multiplier for multiplying sample values by a factor 1/(1-K), where K is a predetermined constant value; a multiplexer having a first input coupled to an output of said first multiplier, and an output; a first delay element coupled to the output of said multiplexer for delaying the sample values each time by one sample clock; a second multiplier coupled to an output of said first delay element for multiplying the delayed sample values by the factor K; an adder having a first input coupled to an output of said second multiplier, and an output coupled to a second input of said multiplexer; a second delay element having an input for also receiving the sample values applied to said first multiplier for delaying said sample values by one sample clock, and an output coupled to a second input of said adder; a subtractor having a first and a second input coupled to the input and the output of said second delay element; a quantity former coupled to an output of said subtractor; and a comparator for comparing an output signal of said quantity former to a predetermined difference value, an output of said comparator being coupled to a control input of said multiplexer, whereby said multiplexer is switched to the first input if said predetermined difference value is exceeded, and otherwise is switched to the second input.