Frame buffer, systems and methods

Claim 2

A buffer, comprising: k input nodes; a sequentially ordered array of k, multiplexing circuits, each multiplexing circuit having a first input coupled to a respective input node; a sequentially ordered array of j transmission gates associated with each multiplexing circuit; first control circuitry for selectively coupling a second input of an (n-2 m-1 )th one of said multiplexing circuits with an output of an n th one of said multiplexing circuits, wherein an mth one of said transmission gates is associated with an (n-2 m-1 )th one of said multiplexing circuits, j, k, m, and n being positive integers, j and k being constants, n being a variable that is greater than 2 m-1 , and m being a variable between 1 and j; second control circuitry coupled to each said multiplexing circuit for selecting between said first and second inputs; and a plurality of outputs coupled to said multiplexing circuits.

Claim 3

The frame buffer of claim 1, wherein said first control circuitry comprises: a plurality of first latches, each said first latch coupled between a respective one of said multiplexers and a respective one of said outputs; and at least one transmission gate coupling an output of a respective said first latch with second inputs of selected ones of said multiplexing circuits.

Claim 4

The frame buffer of claim 2 and further comprising a plurality of second latches, each of said second latches having an input connected to a respective said output of a selected one of said first latches.

Claim 5

The buffer of claim 2, wherein j=4.

Claim 6

The buffer of claim 2, wherein k=32.

Claim 7

The buffer of claim 2, wherein k/j is an integer.

Claim 8

The buffer of claim 2, wherein k/j is a power of 2.

Claim 9

A frame buffer comprising: a sequentially ordered array of k multiplexers, each said multiplexer having first and second data inputs and a data output for passing data appearing at said first data inputs to said data outputs in response to a first control signal and for passing data appearing at said second data inputs to said outputs in response to a second control signal; a sequentially ordered array of k latches, each said latch having an input coupled to said data output of a respective said multiplexer and a latch output, for latching data appearing at said data outputs of said multiplexer; and a sequentially ordered array of j transmission gates, an mth one of said transmission gates associated with an (n-2 m-1 )th one of said multiplexers and operable to couple said second data input of an (n-2 m-1 )th one of said multiplexers with said latch output of an n th one of said latches, wherein j, k, m and n are positive integers, j and k being constants, n being a variable that is greater than 2 m-1 , and m being a variable between 1 and j.

Claim 10

A frame buffer comprising: a sequentially ordered array of k multiplexers, each said multiplexer having first and second data inputs and a data output for passing data appearing at said first data inputs to said data outputs in response to a first control signal and for passing data appearing at said second data inputs to said outputs in response to a second control signal; a sequentially ordered array of k latches, each said latch having an input coupled to said data output of a respective said multiplexer and a latch output, for latching data appearing at said data outputs of said multiplexer; and a sequentially ordered array of j transmission gates, an mth one of said transmission gates associated with an (n-2 m-1 )th one of said multiplexers and operable to couple said second data input of an (n-2 m-1 )th one of said multiplexers with said latch output of an n th one of said latches, wherein j, k, m and n are positive integers, j and k being constants, n being a variable that is greater than 2 m-1 , and m being a variable between 1 and j.

Claim 11

The frame buffer of claim 8, and further comprising: a plurality of second latches for latching data appearing at said latch outputs of selected ones of said plurality of latches.

Claim 12

The frame buffer of claim 9, wherein said plurality of second latches comprises x latches for latching an x bit word, wherein x is a positive integer variable between 1 and 8.

Claim 13

The frame buffer of claim 10 and further comprising a plurality of second multiplexers for selectively outputting an 4 bit nibble of said x bit word latched into said second latches, where 4 is a positive integer <x.

Claim 14

The frame buffer of claim 9, wherein said first latches are operable to latch said data passed to said outputs of said plurality of multiplexers in response to a clocking signal.

Claim 15

The frame buffer of claim 12, wherein said second latches are operable to latch said data appearing at said outputs of said first latches in response to said clocking signal.

Claim 16

The frame buffer of claim 13, wherein said plurality of multiplexers are operable to pass data appearing at said first data inputs to said data outputs in response said first control signal and operable to switch to pass data appearing at second data inputs in response to a first one of a sequence of said clocking signals occurring after said first control signal.

Claim 17

A color palette comprising: a first memory having a plurality of locations for containing a plurality of color codes; a second memory having a plurality of locations containing a plurality of color data words; a frame buffer operable to receive a selected one of said color codes from said first memory and output an address to said second memory in response, said address identifying a selected said location in said second memory containing a said selected color data word, said frame buffer comprising: a sequentially ordered array of r multiplexers each having first and second data inputs and a data output and operable to pass data appearing at said first data input in response to a control signal and operable to pass data appearing at said second data input in response to a first one of a sequence of clocking signals occurring after said control signal; a sequentially ordered array of r multiplexers, each said latch having an input coupled to said output of a respective said multiplexer and a latch output, said plurality of latches operable to latch data appearing at said outputs of said multiplexers to said latch outputs in response to said sequence of clocking signals; and a sequentially ordered array of j transmission gates, an mth one of said transmission gates associated with an (n-2 m-1 )th one of said multiplexers and operable to couple said second data input of an (n-2 m-1 )th one of said multiplexers with said latch output of an n th one of said latches, where j, r, m and n are positive integers, j and r being constants, m being a variable between 1 and j, and n being a variable that is greater than 2 m-1 .

Claim 18

A color palette comprising: a first memory having a plurality of locations for containing a plurality of color codes; a second memory having a plurality of locations containing a plurality of color data words; a frame buffer operable to receive a selected one of said color codes from said first memory and output an address to said second memory in response, said address identifying a selected said location in said second memory containing a said selected color data word, said frame buffer comprising: a sequentially ordered array of r multiplexers each having first and second data inputs and a data output and operable to pass data appearing at said first data input in response to a control signal and operable to pass data appearing at said second data input in response to a first one of a sequence of clocking signals occurring after said control signal; a sequentially ordered array of r multiplexers, each said latch having an input coupled to said output of a respective said multiplexer and a latch output, said plurality of latches operable to latch data appearing at said outputs of said multiplexers to said latch outputs in response to said sequence of clocking signals; and a sequentially ordered array of j transmission gates, an mth one of said transmission gates associated with an (n-2 m-1 )th one of said multiplexers and operable to couple said second data input of an (n-2 m-1 )th one of said multiplexers with said latch output of an n th one of said latches, where j, r, m and n are positive integers, j and r being constants, m being a variable between 1 and j, and n being a variable that is greater than 2 m-1 .

Claim 19

The color palette of claim 15 and further comprising a plurality of second latches having inputs coupled to said outputs of selected ones of said latches.