Abstract In a preplacement method for use in a computer-assisted integrated design layout process, circuit entities are placed by a computer program on a layout of an integrated circuit stored in computer memory. The circuit to be laid out is represented in computer memory as circuit entities interconnected between pins on the circuit entities. A set of pins to be interconnected forms a net and is assigned a weight. The method allows a user to cause the computer program to place a circuit entity at a different location on the integrated circuit layout than it would otherwise. A faked two pin net is defined, one pin being located on the circuit entity and another pin being located in a region of the integrated circuit in which the user desires the circuit entity to be placed. A high weight is then assigned to the faked two pin net that is much greater than weights assigned to other nets in the integrated circuit layout. The computer program then places the circuit entity in the region of the other pin in accordance with the high weight assigned to the faked net.
In a computer-assisted integrated circuit design layout process in which circuit entities are placed by a computer program on a layout of an integrated circuit stored in computer memory, a circuit to be laid out being represented in computer memory as circuit entities interconnected between pins on the circuit entities, a set of pins to be interconnected forming a net having a weight assigned thereto, a method of preplacing circuit entities whereby the computer program is caused to place a circuit entity at a different location on the integrated circuit layout than the computer program would otherwise place the circuit entity at, comprising the steps of: defining a faked two-pin net, one pin being located within said circuit entity and another pin being located in a region of the integrated circuit, approximately the size of said circuit entry, in which the circuit is to be placed; assigning a weight W F to said faked two-pin net that is greater than weights assigned to other nets in the integrated circuit layout; the computer program then placing said circuit entity at least partially within said region of said another pin in accordance with said weight W F and said weights assigned other nets in the integrated circuit layout; and building the integrated circuit.
Claim 2
Dependent Claim
211 words
In a computer-assisted integrated circuit design layout process in which circuit entities are placed by a computer program on a layout of an integrated circuit stored in computer memory, a circuit to be laid out being represented in computer memory as circuit entities interconnected between pins on the circuit entities, a set of pins to be interconnected forming a net having a weight assigned thereto, a method of preplacing circuit entities whereby the computer program is caused to place a circuit entity at a different location on the integrated circuit layout than the computer program would otherwise place the circuit entity at, comprising the steps of: defining a faked two-pin net, one pin being located within said circuit entity and another pin being located in a region of the integrated circuit, approximately the size of said circuit entry, in which the circuit is to be placed; assigning a weight W F to said faked two-pin net that is greater than weights assigned to other nets in the integrated circuit layout; the computer program then placing said circuit entity at least partially within said region of said another pin in accordance with said weight W F and said weights assigned other nets in the integrated circuit layout; and building the integrated circuit.