Patent US5305281A successfully refreshed from Google Patents.
US5305281A
Expired / Lapsed
US
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Multiple array memory device with staggered read/write for high speed data access
Assignee: National Semiconductor Corp
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Filing: 1992-08-06
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Granted: 1994-04-19
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Expires: 2012-08-06
Abstract
Abstract A multiple array memory device formed on a single IC chip performing transfers of a series of data between the device and its interface at high speed. The device includes a memory having a plurality of groups of memory arrays. In a read operation, the device internally reads data from sequential locations starting at any desired address and extending across the memory arrays into a latch. As the data are output to the interface from the latch, sequential data from an adjacent group of array in the memory are internally read into the latch. Thus, a series of data can be output to the interface at high speed. The write operation is performed in a similar manner.
Inventors
- 👤 Paul R. Lubeck
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 12:41
CPC Classifications
G; G11; G11C; G11C7/00; G11C7/10; G11C7/1015; G11C7/103; G11C5/00; G11C5/02; G11C5/025
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
295 words
A multiple array memory device including memory and a data transfer path and formed on a single chip for allowing high speed transfers of a series of data between the memory and the data transfer path, comprising: the memory having a plurality of groups of memory arrays; means, coupled to said memory, for holding data to be transferred between said memory and the data transfer path; and means, coupled to said memory and said holding means, for controlling said memory and said holding means for transferring data between said memory and the data transfer path so that data transfers with respect to a selected number of sequential memory locations in said memory can be performed alternately between said memory and said holding means and between said holding means and the data transfer path wherein the data transfers with respect to said selected number of sequential memory locations are performed alternately on a group-by-group basis, thereby allowing sequential transfers of the series of data between said selected number of sequential memory locations and the data transfer path and wherein in a read cycle said controlling means causes data in said memory to be internally read into said holding means and on an alternate basis said controlling means causes data in said holding means to be output to the data transfer path, so that when data received from a group of arrays and held in said holding means are output to the data transfer path, sequential data in another group of arrays are internally read into said holding means if said sequential data are not being held in said holding means, whereby said controlling means can cause any desired number of sequential data to be output from said memory to the data transfer path at high speed.
Claim 2
Dependent Claim
295 words
A multiple array memory device including memory and a data transfer path and formed on a single chip for allowing high speed transfers of a series of data between the memory and the data transfer path, comprising: the memory having a plurality of groups of memory arrays; means, coupled to said memory, for holding data to be transferred between said memory and the data transfer path; and means, coupled to said memory and said holding means, for controlling said memory and said holding means for transferring data between said memory and the data transfer path so that data transfers with respect to a selected number of sequential memory locations in said memory can be performed alternately between said memory and said holding means and between said holding means and the data transfer path wherein the data transfers with respect to said selected number of sequential memory locations are performed alternately on a group-by-group basis, thereby allowing sequential transfers of the series of data between said selected number of sequential memory locations and the data transfer path and wherein in a read cycle said controlling means causes data in said memory to be internally read into said holding means and on an alternate basis said controlling means causes data in said holding means to be output to the data transfer path, so that when data received from a group of arrays and held in said holding means are output to the data transfer path, sequential data in another group of arrays are internally read into said holding means if said sequential data are not being held in said holding means, whereby said controlling means can cause any desired number of sequential data to be output from said memory to the data transfer path at high speed.
Claim 3
Dependent Claim
41 words
A multiple array memory device according to claim 1 wherein during an initial read said controlling means causes data in sequential locations starting at any desired address and extending across said memory arrays to be internally read into said holding means.
Claim 4
Dependent Claim
121 words
A multiple array memory device according to claim 1 wherein in a write cycle said controlling means causes data from the data transfer path to be input into said holding means and on an alternate basis said controlling means causes data in said holding means to be internally written into said memory, so that when data for a corresponding group of arrays of said memory are written into said memory, sequential data for another group of arrays are input into said holding means if said sequential data are not being held in said holding means, whereby said controlling means can cause any desired number of sequential data to be input into said memory from the data transfer path at high speed.
Claim 5
Dependent Claim
43 words
A multiple array memory device according to claim 3 wherein during an initial write said controlling means causes sequential data for any group of memory arrays beginning at any desired address to be input into said holding means from the data transfer path.
Claim 6
Dependent Claim
293 words
A multiple array memory device including a memory and a data transfer path and formed on a single chip for allowing high speed transfers of a series of data between the memory and the data transfer path, comprising: the memory having a plurality of groups of memory arrays; buffer means, coupled to said memory, for holding data to be transferred between said memory and the data transfer path; select means, coupled to said buffer means, for selectively transferring data between said buffer means and the data transfer path, and control means, coupled to said memory and said select means, for controlling said memory and said select means for transferring data between said memory and the data transfer path so that data transfers with respect to a selected number of sequential memory locations in said memory can be performed alternately on a group-by-group basis between said memory and said buffer means and between said buffer means and the data transfer path, thereby allowing sequential transfers of the series of data between said selected number of sequential memory locations and the data transfer path wherein in a read cycle said control means causes data in said memory to be internally read into said buffer means and on an alternate basis said select means outputs data in said buffer means to the data transfer path, so that when said select means outputs data received from a group of arrays to the data transfer path, sequential data in another group of arrays are internally read into said buffer means if said sequential data are not being held in said buffer means, whereby said control means can cause any desired number of sequential data to be output from said memory to the data transfer path at high speed.
Claim 7
Dependent Claim
293 words
A multiple array memory device including a memory and a data transfer path and formed on a single chip for allowing high speed transfers of a series of data between the memory and the data transfer path, comprising: the memory having a plurality of groups of memory arrays; buffer means, coupled to said memory, for holding data to be transferred between said memory and the data transfer path; select means, coupled to said buffer means, for selectively transferring data between said buffer means and the data transfer path, and control means, coupled to said memory and said select means, for controlling said memory and said select means for transferring data between said memory and the data transfer path so that data transfers with respect to a selected number of sequential memory locations in said memory can be performed alternately on a group-by-group basis between said memory and said buffer means and between said buffer means and the data transfer path, thereby allowing sequential transfers of the series of data between said selected number of sequential memory locations and the data transfer path wherein in a read cycle said control means causes data in said memory to be internally read into said buffer means and on an alternate basis said select means outputs data in said buffer means to the data transfer path, so that when said select means outputs data received from a group of arrays to the data transfer path, sequential data in another group of arrays are internally read into said buffer means if said sequential data are not being held in said buffer means, whereby said control means can cause any desired number of sequential data to be output from said memory to the data transfer path at high speed.
Claim 8
Dependent Claim
41 words
A multiple array memory device according to claim 5 wherein during an initial read said control means causes data in sequential locations starting at any desired address and extending across said memory arrays to be internally read into said buffer means.
Claim 9
Dependent Claim
123 words
A multiple array memory device according to claim 5 wherein in a write cycle said select means inputs data into said buffer means and on an alternate basis said control means causes data in said buffer means to be internally written into said memory so that when data for a corresponding group of arrays of said memory are written into said memory, said select means inputs sequential data from the data transfer path into said buffer means to be written into another group of arrays if said sequential data are not being held in said buffer means, whereby said control means can cause any desired number of sequential data to be input into said memory from the data transfer path at high speed.
Claim 10
Dependent Claim
43 words
A multiple array memory device according to claim 7 wherein during an initial write said select means inputs sequential data from the data transfer path into said buffer means to be written into a group of memory arrays beginning at any desired address.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1997-04-18 | 1997-10-18 | 1998-04-19 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-04-18 | 2001-10-18 | 2002-04-19 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-04-18 | 2005-10-18 | 2006-04-19 | $7700.00 | Window Closed / Lapsed |