Static random access memory cell with single logic-high voltage level bit-line and address-line drivers

Claim 1

A memory cell comprising: first and second cross-coupled inverters coupled to a bit line through a pass transistor, said first cross-coupled inverter including a first P-Channel MOS transistor having a source connected to a first power supply node, a gate, and a drain, and a first N-Channel MOS transistor having a gate, a drain connected to the drain of said first P-Channel MOS transistor and forming an output node, and a source connected to a second power supply node, said second cross-coupled inverter including a second P-Channel MOS transistor having a source connected to said first power supply node, a gate, and a drain, and a second N-Channel MOS transistor having a drain connected to the drain of said second P-Channel MOS transistor and forming an internal node, a source connected to said second power supply node, and a gate, the gates of said first N-Channel and P-Channel MOS transistors connected to said internal node and the gates of said second N-Channel and P-Channel MOS transistors connected to said output node; means for providing a first voltage supply potential to said first power supply node during a read operation of the memory cell, and for providing a second voltage supply potential to said first power supply node during a write operation to the memory cell, the second voltage supply potential having a value less than the first voltage supply potential; and wherein the magnitudes of said first and second voltage supply potentials and wherein said pass transistor and said first N-Channel MOS transistor have channel lengths and widths selected such that the voltage at said output node remains below an N-Channel threshold voltage during a read operation of a logic zero at said output node while said memory cell is powered by said first voltage supply potential, and that the voltage at said output node remains above an N-Channel threshold voltage during a write operation of a logic one at said output node while said memory cell is powered by said second voltage supply potential.