Abstract A radiation hard memory cell comprises on an insulating substrate a low output impedance inverter made of a monocrystalline semiconductor and a high output impedance inverter made of a non-crystalline semiconductor in order to save space. The semiconductor can be Si and a barrier layer can be used. A method for making the cell comprises depositing and defining active layers, making gate insulating layers on the active layers, forming gates on the insulating layers, and forming source and drain regions in the active layers. One inverter can have its active and insulating layers formed before the remaining active layer is formed. The remaining active layer can then be simultaneously formed with the gate of the one active layer.
A memory cell comprising: a first inverter having a low output impedance and comprising a pair of field effect transistors each having source, drain, and channel regions of a monocrystalline semiconductor; and a second inverter, cross-coupled to said first inverter, said second inverter having a high output impedance and comprising a pair of field effect transistors each having source, drain and channel regions of a non-monocrystalline semiconductor, wherein the area occupied by the second inverter having a high output impedance is smaller than the area occupied by the first inverter having a low output impedance.
Claim 2
Dependent Claim
95 words
A memory cell comprising: a first inverter having a low output impedance and comprising a pair of field effect transistors each having source, drain, and channel regions of a monocrystalline semiconductor; and a second inverter, cross-coupled to said first inverter, said second inverter having a high output impedance and comprising a pair of field effect transistors each having source, drain and channel regions of a non-monocrystalline semiconductor, wherein the area occupied by the second inverter having a high output impedance is smaller than the area occupied by the first inverter having a low output impedance.
Claim 3
Dependent Claim
14 words
The memory cell of claim 1 wherein said non-monocrystalline semiconductor comprises a polycrystalline semiconductor.
Claim 4
Dependent Claim
13 words
The memory cell of claim 1 wherein each of said semiconductors comprises silicon.
Claim 5
Dependent Claim
32 words
The memory cell of claim 1 further comprising a substrate means for supporting said inverters disposed proximate said inverters, and an insulating barrier layer disposed between said second invertor and said substrate.