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US5300822A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Power-on-reset circuit
Assignee: NEC Electronics Corp
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Filing: 1992-12-28
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Granted: 1994-04-05
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Expires: 2012-12-28
Abstract
Abstract A power-on-reset circuit includes a plurality of MOS transistors and a first depletion type N-channel MOS transistor connected in series to an input terminal of a current mirror circuit. A capacitor is connected between the input terminal and a voltage supply terminal. A second depletion type N-channel MOS transistor having a low current driving capacity is connected to an output terminal of the current mirror circuit. The degree of integration can be increased by constituting an integrating circuit with depletion type N-channel MOS transistors in place of a resistor. In addition, the voltage supply voltage is compared to the sum of the threshold voltage of the plurality of MOS transistors. This makes it possible to initialize the internal circuit positively even if the rise time of the voltage supply voltage becomes larger than the time constant of the integrating circuit.
Inventors
- 👤 Eiichi Sugahara
- 👤 Takashi Fujii
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 13:56
CPC Classifications
H; H03; H03K; H03K17/00; H03K17/22; H03K17/223
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
183 words
A power-on-reset circuit comprising: a current mirror circuit connected to a first voltage supply; a first depletion type transistor which has its source connected to a second voltage supply, and which operates as a constant current source; a second depletion type transistor which has its drain connected to an output terminal of said current mirror circuit and its source connected to said second voltage supply, and which operates as a constant current source; an integrating capacitor connected at its end to an input terminal of said current mirror circuit and at its other end to said first voltage supply; an N-channel MOS transistor having its gate connected to said first voltage supply and its drain connected to said input terminal of said current mirror circuit; and a P-channel MOS transistor having its gate connected to said second voltage supply, its source connected to a source of said N-channel MOS transistor, and its drain connected to a drain of said first depletion type transistor; an output current of said current mirror circuit being larger than a driving current of said second depletion type transistor.
Claim 2
Dependent Claim
183 words
A power-on-reset circuit comprising: a current mirror circuit connected to a first voltage supply; a first depletion type transistor which has its source connected to a second voltage supply, and which operates as a constant current source; a second depletion type transistor which has its drain connected to an output terminal of said current mirror circuit and its source connected to said second voltage supply, and which operates as a constant current source; an integrating capacitor connected at its end to an input terminal of said current mirror circuit and at its other end to said first voltage supply; an N-channel MOS transistor having its gate connected to said first voltage supply and its drain connected to said input terminal of said current mirror circuit; and a P-channel MOS transistor having its gate connected to said second voltage supply, its source connected to a source of said N-channel MOS transistor, and its drain connected to a drain of said first depletion type transistor; an output current of said current mirror circuit being larger than a driving current of said second depletion type transistor.
Claim 3
Dependent Claim
232 words
A power-on-reset circuit comprising; a current mirror circuit connected to a first voltage supply; a first depletion type transistor which has its source connected to a second voltage supply, and which operates as a constant current source; a second depletion type transistor which has its drain connected to an output terminal of said current mirror circuit and its source connected to said second voltage supply, and which operates as a constant current source; an integrating capacitor connected at its end to an input terminal of said current mirror circuit and at its other end to said first voltage supply; and at least one MOS transistor connected at its one end to an input terminal of said current mirror circuit and at its other end to a drain of said first depletion type transistor, a voltage representative of a voltage between said first voltage supply and said second voltage supply being applied between a gate and a source of said at least one MOS transistor; an output current of said current mirror circuit being larger than a driving current of said second depletion type transistor; wherein, said at least one MOS transistor is constituted of a P-channel MOS transistor having its gate connected to said second voltage supply, its source connected to said input terminal of said current mirror circuit and its drain connected to a drain of said first depletion type transistor.
Claim 4
Dependent Claim
232 words
A power-on-reset circuit comprising; a current mirror circuit connected to a first voltage supply; a first depletion type transistor which has its source connected to a second voltage supply, and which operates as a constant current source; a second depletion type transistor which has its drain connected to an output terminal of said current mirror circuit and its source connected to said second voltage supply, and which operates as a constant current source; an integrating capacitor connected at its end to an input terminal of said current mirror circuit and at its other end to said first voltage supply; and at least one MOS transistor connected at its one end to an input terminal of said current mirror circuit and at its other end to a drain of said first depletion type transistor, a voltage representative of a voltage between said first voltage supply and said second voltage supply being applied between a gate and a source of said at least one MOS transistor; an output current of said current mirror circuit being larger than a driving current of said second depletion type transistor; wherein, said at least one MOS transistor is constituted of a P-channel MOS transistor having its gate connected to said second voltage supply, its source connected to said input terminal of said current mirror circuit and its drain connected to a drain of said first depletion type transistor.
Claim 5
Dependent Claim
232 words
A power-on-reset circuit comprising; a current mirror circuit connected to a first voltage supply; a first depletion type transistor which has its source connected to a second voltage supply, and which operates as a constant current source; a second depletion type transistor which has its drain connected to an output terminal of said current mirror circuit and its source connected to said second voltage supply, and which operates as a constant current source; an integrating capacitor connected at its end to an input terminal of said current mirror circuit and at its other end to said first voltage supply; and at least one MOS transistor connected at its one end to an input terminal of said current mirror circuit and at its other end to a drain of said first depletion type transistor, a voltage representative of a voltage between said first voltage supply and said second voltage supply being applied between a gate and a source of said at least one MOS transistor; an output current of said current mirror circuit being larger than a driving current of said second depletion type transistor; wherein, said at least one MOS transistor is constituted of an N-channel MOS transistor having its gate and its drain short-circuited to each other and connected to said input terminal of said current mirror circuit and its source connected to a drain of said first depletion type transistor.
Claim 6
Dependent Claim
232 words
A power-on-reset circuit comprising; a current mirror circuit connected to a first voltage supply; a first depletion type transistor which has its source connected to a second voltage supply, and which operates as a constant current source; a second depletion type transistor which has its drain connected to an output terminal of said current mirror circuit and its source connected to said second voltage supply, and which operates as a constant current source; an integrating capacitor connected at its end to an input terminal of said current mirror circuit and at its other end to said first voltage supply; and at least one MOS transistor connected at its one end to an input terminal of said current mirror circuit and at its other end to a drain of said first depletion type transistor, a voltage representative of a voltage between said first voltage supply and said second voltage supply being applied between a gate and a source of said at least one MOS transistor; an output current of said current mirror circuit being larger than a driving current of said second depletion type transistor; wherein, said at least one MOS transistor is constituted of an N-channel MOS transistor having its gate and its drain short-circuited to each other and connected to said input terminal of said current mirror circuit and its source connected to a drain of said first depletion type transistor.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1997-04-04 | 1997-10-04 | 1998-04-05 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-04-04 | 2001-10-04 | 2002-04-05 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-04-04 | 2005-10-04 | 2006-04-05 | $7700.00 | Window Closed / Lapsed |