Metal-to-metal antifuse structure

Claim 1

A method of forming an antifuse structure on a semiconductor device comprising the steps of: a. depositing a first layer of conducting material on said semiconductor device; b. depositing a dielectric layer over said first conducting layer; c. depositing an etchstop layer over said dielectric layer; d. etching said etchstop layer, said dielectric layer, and said first metal layer to form an antifuse stack; e. depositing a layer of interlevel oxide over said antifuse stack and said semiconductor device; f. etching an antifuse via in said interlevel dielectric layer to expose a portion of said antifuse stack, wherein said antifuse via extends through said interlevel dielectric layer to said antifuse stack; g. removing a portion of said etchstop layer located at said antifuse via to expose a portion of said dielectric layer; h. depositing a second layer of conducting material over said interlevel dielectric layer, and said exposed portion of said dielectric layer such that said second conducting layer fills said antifuse via; and i. etching said second conducting layer.

Claim 2

A method of forming an antifuse structure on a semiconductor device comprising the steps of: a. depositing a first layer of conducting material on said semiconductor device; b. depositing a dielectric layer over said first conducting layer; c. depositing an etchstop layer over said dielectric layer; d. etching said etchstop layer, said dielectric layer, and said first metal layer to form an antifuse stack; e. depositing a layer of interlevel oxide over said antifuse stack and said semiconductor device; f. etching an antifuse via in said interlevel dielectric layer to expose a portion of said antifuse stack, wherein said antifuse via extends through said interlevel dielectric layer to said antifuse stack; g. removing a portion of said etchstop layer located at said antifuse via to expose a portion of said dielectric layer; h. depositing a second layer of conducting material over said interlevel dielectric layer, and said exposed portion of said dielectric layer such that said second conducting layer fills said antifuse via; and i. etching said second conducting layer.

Claim 15

A method of forming a metal-to-metal antifuse structure on a semiconductor device comprising the steps of: a. depositing a first layer of metal on said semiconductor device, wherein said first metal layer comprises a metal that will not react with amorphous silicon or aluminum-silicon-copper; b. depositing a dielectric layer over said first metal layer, wherein said dielectric layer comprises amorphous silicon; c. depositing a layer of oxide over said dielectric layer; d. depositing a layer of amorphous silicon over said oxide layer e. etching said amorphous silicon layer, said oxide layer, said dielectric layer, and said first metal layer to form an antifuse stack; f. depositing a layer of interlevel oxide over said antifuse stack and said semiconductor device; g. etching a first and a second via in said interlevel dielectric layer to expose a portion of said semiconductor device and a portion of said antifuse stack, wherein said first via extends through said interlevel dielectric layer to said semiconductor device and said second via extends through said interlevel dielectric layer to said antifuse stack; h. etching a portion of said amorphous silicon layer located at said second via to expose a portion of said oxide layer; i. etching a portion of said oxide layer located at said second via to expose a portion of said dielectric layer; j. depositing a second layer of metal over said interlevel dielectric layer, said exposed portion of said semiconductor device and said exposed portion of said dielectric layer such that said second metal layer fills said first and second vias; and k. etching said second metal layer.

Claim 16

A method of forming a metal-to-metal antifuse structure on a semiconductor device comprising the steps of: a. depositing a first layer of metal on said semiconductor device, wherein said first metal layer comprises a metal that will not react with amorphous silicon or aluminum-silicon-copper; b. depositing a dielectric layer over said first metal layer, wherein said dielectric layer comprises amorphous silicon; c. depositing a layer of oxide over said dielectric layer; d. depositing a layer of amorphous silicon over said oxide layer e. etching said amorphous silicon layer, said oxide layer, said dielectric layer, and said first metal layer to form an antifuse stack; f. depositing a layer of interlevel oxide over said antifuse stack and said semiconductor device; g. etching a first and a second via in said interlevel dielectric layer to expose a portion of said semiconductor device and a portion of said antifuse stack, wherein said first via extends through said interlevel dielectric layer to said semiconductor device and said second via extends through said interlevel dielectric layer to said antifuse stack; h. etching a portion of said amorphous silicon layer located at said second via to expose a portion of said oxide layer; i. etching a portion of said oxide layer located at said second via to expose a portion of said dielectric layer; j. depositing a second layer of metal over said interlevel dielectric layer, said exposed portion of said semiconductor device and said exposed portion of said dielectric layer such that said second metal layer fills said first and second vias; and k. etching said second metal layer.