Preemption control for central processor with cache

Claim 1

In a computer system having a data bus and plural masters, including a main processor, connected thereto which contend for said data bus using bus request signals transmitted over a signal path connecting said masters to arbitration control logic which identifies, by a device identifying signal on an arbitration bus of said computer system, a current bus owner, said system having a memory cache system connected to said data bus to cooperate with said main processor to provide data from a cache buffer which includes first means to provide a first logic signal for each instance when such data is provided, a preference circuit for the main processor comprising: second means connected to receive said device identifying signal for detecting intervals in which said main processor is identified as owner of the data bus and for generating a second logic signal during such interval; third means connected to said first means for receiving and counting said first logic signals and producing a third logic signal when a predefined count is reached; a gate connected to receive said second and third logic signals and included in said signal path ahead of said arbitration control logic to intercept said bus request signals, which gate blocks said bus request signals when said second logic signal is active while said third logic signal is not active and otherwise passes said bus request signal to said arbitration control logic.