Time sharing device for access to a main memory through to a single bus connected between a central computer and a plurality of peripheral computers

Claim 1

A time sharing device in a system having a principal memory connected to a single bus, said single bus also being connected to a central computer and a plurality of peripheral computers and in which the central computer is normally occupying said bus to communicate through said bus to said memory, said time sharing device comprising: searching circuit means connected to said peripheral computers in a bidirectional manner for cyclically accessing said peripheral computers in a predetermined order and receiving requests to use said single bus from an accessed computer, and for identifying the peripheral computer making a request; decision circuit means connected to said searching circuit means and connected in a bidirectional manner to said central computer and said peripheral computers for receiving information from said central computer and said peripheral computers concerning the state of occupancy of said single bus and granting authorization to the peripheral computer making a request only when said single bus is free and use of the single bus is not required by the central computer; and wherein said searching circuit includes a cyclic counter, a multiplexer and a flip-flop, said multiplexer being controlled by said cyclic counter the cycle whereof depends on the number of the said peripheral computers being connected to said bus, said cyclic counter having an address output connected to said peripheral computers, said multiplexer having inputs connected, respectively, to said peripheral computers, an output connected to a set input of said flip-flop, said flip-flop being connected to said cyclic counter so that said cyclic counter is inhibited on the output connected to the peripheral computer having requested to use said bus, said flip-flop also being connected to an input of said decision circuit for transmitting a signal to said decision circuit indicating that a request is being received, an output of said decision circuit being connected with a reset input of said flip-flop so as to return the said flip-flop to its initial state, and to a control input of said cyclic counter in order to return said cyclic counter to service when authorization to use said bus has been granted by said decision circuit.