Modular multiprocessor system with recirculating priority

Claim 2

A modular computer system comprising a plurality of processors, a plurality of peripheral devices, a common bus providing an electrical signal path and having a plurality of connection points along the length of the bus to which the processors and peripheral devices are respectively connected means in each of the processors for applying when activated a binary coded address signal to the common bus, means in each of the peripheral devices for decoding the address signal on the common bus for selectively activating particular ones of the peripheral devices in response to the decoded address signals, the activated peripheral devices communicating with the processors over said common bus, and priority means for controlling the address signal coupling means in each of the processors, said priority means including means for activating the address signal coupling means in one processor at a time.

Claim 3

Apparatus as defined in claim 1 wherein said priority means further includes means for activating said address signal coupling means in each processor in sequence.

Claim 4

Apparatus as defined in claim 1 wherein the priority means includes, in each processor, means for storing a binary bit, means for transmitting said bit in the associated processor to another processor, said means for activating the address signal coupling means including means responsive to the presence of said bit in the storing means of a particular processor for activating the address signal coupling means in that processor.

Claim 5

A modular computer system in which a plurality of processors are arranged to individually transfer signals to or from a plurality of remote devices over a common bus, comprising, in each processor, means for storing a group of bits identifying any selected one of the remote devices, means generating an output signal indicating that a transfer is required, a priority control flip-flop generating an output signal indicating that the associated processor has priority, means responsive to the transfer signal and the priority signal for gating the contents of said storing means to each of the remote devices over said common bus, means connecting the priority flip-flop of each processor to the next processor to form a closed ring, means successively turning each of the flip-flops in the ring on and off with only one flip-flop being on at a time, and means responsive to said output signal when it indicates a transfer is required in a particular processor for inhibiting the turning off of the associated priority flip-flop until the transfer is complete.

Claim 6

A modular computer system in which a plurality of processors are arranged to individually transfer signals to or from a plurality of remote devices over a common bus, comprising, in each processor, means for storing a group of bits identifying any selected one of the remote devices, means generating an output signal indicating that a transfer is required, a priority control flip-flop generating an output signal indicating that the associated processor has priority, means responsive to the transfer signal and the priority signal for gating the contents of said storing means to each of the remote devices over said common bus, means connecting the priority flip-flop of each processor to the next processor to form a closed ring, means successively turning each of the flip-flops in the ring on and off with only one flip-flop being on at a time, and means responsive to said output signal when it indicates a transfer is required in a particular processor for inhibiting the turning off of the associated priority flip-flop until the transfer is complete.