Multiplex data processing system

Claim 1

A multiplex data processing system comprising: two or more data processing units; a shared memory device connected to the data processing units for storing data processed by any one of the data processing units; and a job registration unit connected to the shared memory device for accepting and storing job request information including priority order information for determining the priority level of the job request information, for transferring the job request information with the determined priority level to the shared memory device and for supplying an interrupt signal to the data processing units to control the data processing units so that they execute jobs according to the job request information stored in the shared memory device; said job registration unit comprising a memory circuit for storing job request information, an address generator for generating an address signal which designates a memory location of the shared memory device corresponding to the job request information with highest piority level, a request circuit for generating a signal for requesting from the shared memory device the use of the shared memory device, a data register for storing the logical sum of the data stored in the memory location designated by the address signal and the job request information with highest priority level, a read/write control circuit for designating any one of a read cycle for reading each information bit of data at the memory location designated by the address signal from the shared memory device into the data register and a write cycle for writing the respective information bit of the logical sum of the data stored in the memory location designated by the address signal and the job request information with highest priority level from the data register into the shared memory device, an interrupt signal generator responsive to the writing from the data register into the shared memory device for generating an interrupt signal which is applied to the data processing units to cause the job to be executed by the interrupted data processor indicated by the job request information which is stored in the shared memory device, and a sequence control circuit for controlling the memory circuit, address generator, request circuit, read/write control circuit, data register and interrupt signal generator.