Write circuit for non-volatile memory device

Claim 1

A write circuit for a non-volatile memory device including a plurality of cell transistors, each of said cell transistors being connected to one of a plurality of bit lines, and a bit line select transistor provided with respect to each bit line and which supplies a source current thereof to one of the cell transistors, as a drain current of the cell transistor, via a corresponding one of the bit lines, said write circuit comprising: a dummy cell transistor which detects a breakdown voltage of the cell transistor in a write mode; circuit means, coupled to said dummy cell transistor and responsive to a write mode signal which is indicative of the write mode, for varying the gate voltage of the bit line select transistor as a function of the breakdown voltage detected by said dummy cell transistor and thereby to make the gate-source voltage of the bit line select transistor approximately constant, so that the drain current of the cell transistor during the write mode is maintained approximately constant; and the non-volatile memory device further comprising a row decoder connected to the word lines and which selects one of the word lines in response to an address signal, a column decoder connected to the bit lines and which selects one of the bit lines in response to the address signal, and a sense amplifier which senses and amplifies information read out from the cell transistors, said bit line select transistor being provided within said column decoder and said circuit means supplying a power source voltage for said column decoder.