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Patent US5293336A successfully refreshed from Google Patents.
US5293336A
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Semiconductor memory device and method for manufacturing the same
Assignee: Toshiba Corp
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Filing: 1991-10-29
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Granted: 1994-03-08
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Expires: 2011-10-29
Abstract
Abstract A semiconductor memory device has a memory cell composed of a select MOS transistor and information storage capacitor and a peripheral circuit composed of a MOS transistor formed at a peripheral side of the memory cell, these transistors being formed in the surface portion of a first conductivity type semiconductor substrate. In the semiconductor memory device, the gate oxide film of the select MOS transistor is different in thickness from the gate oxide film of the MOS transistor of the peripheral circuit, the gate electrodes of these transistors being simultaneously formed.
Inventors
- 👤 Takeaki Ishii
- 👤 Satoshi Maeda
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 19:52
CPC Classifications
H; H10; H10B; H10B12/00; H10B12/30; H10B12/33; H10B12/01; H10B12/02; H10B12/03; H10B12/033; H10B12/05; H10D; H10D84/00; H10D84/01; H10D84/0123; H10D84/0126; H10D84/0144; H10D84/02; H10D84/03; H10D84/038
Claims Analysis
Total Claims: 2
Claim 1
Independent Claim
106 words
A semiconductor memory device comprising: a memory cell composed of a select MOS transistor and an information storage capacitor both formed on a surface portion of a first conductivity type semiconductor region of a substrate and a peripheral circuit composed of a MOS transistor formed on the surface portion of the semiconductor region of the substrate at a peripheral portion of the memory cell, wherein a thickness of a gate oxide film of the MOS transistor of the peripheral circuit is between a thickness of a gate oxide film of the select MOS transistor and a thickness of an insulating film of the information storage capacitor.
Claim 2
Dependent Claim
106 words
A semiconductor memory device comprising: a memory cell composed of a select MOS transistor and an information storage capacitor both formed on a surface portion of a first conductivity type semiconductor region of a substrate and a peripheral circuit composed of a MOS transistor formed on the surface portion of the semiconductor region of the substrate at a peripheral portion of the memory cell, wherein a thickness of a gate oxide film of the MOS transistor of the peripheral circuit is between a thickness of a gate oxide film of the select MOS transistor and a thickness of an insulating film of the information storage capacitor.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1997-03-07 | 1997-09-06 | 1998-03-08 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-03-07 | 2001-09-06 | 2002-03-08 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-03-07 | 2005-09-06 | 2006-03-08 | $7700.00 | Window Closed / Lapsed |