US5083172A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Dynamic random access memory device fabricated with two kinds of field effect transistor different in thickness of gate oxide films
Assignee: NEC Corp
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Filing: 1991-01-25
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Granted: 1992-01-21
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Expires: 2011-01-25
Abstract
Abstract A dynamic random access memory device comprises memory cells each implemented by a series combination of a switching transistor and a storage capacitor, peripheral circuits fabricated with component field effect transistors, and word lines coupled to the gate electrodes of the switching transistors, and the gate oxide film of each switching transistor is thicker than the gate oxide film of each component field effect transistor, wherein the word lines are coupled through an oxide film thinner than the gate oxide film of the switching transistor to an impurity region so that undersirable electric charges accumulated in the word lines during the fabrication process are discharged to the impurity region before any damages take place in the gate oxide films of the switching transistors.
Inventors
- 👤 Junji Kiyono
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-06 06:01
CPC Classifications
H; H10; H10B; H10B12/00; H10B12/30
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
219 words
A dynamic random access memory device fabricated on a semiconductor substrate, comprising: a) a plurality of memory cells each implemented by a series combination of a switching transistor and a storage capacitor, said switching transistor being formed by a field effect transistor with a first gate insulating film; b) a plurality of peripheral units provided in association with said memory cells and including a first power source circuit supplied with a power voltage level for distributing the power voltage level, and a second power source circuit supplied with said power voltage level for supplying a higher voltage level than said power voltage level, one of said peripheral units being fabricated from component field effect transistors each having a second gate insulating film thinner than said first gate insulating film, a gate electrode formed on said second gate insulating film being supplied with said power voltage level; c) a plurality of word lines coupled to said memory cells, one of said word lines being coupled to a gate electrode formed on said first gate insulating film, said gate electrode on said first gate insulating film being supplied with said higher voltage level; and d) discharging means formed in said semiconductor substrate and coupled to each of said word lines through an insulating film thinner than said first gate insulating film.
Claim 2
Dependent Claim
219 words
A dynamic random access memory device fabricated on a semiconductor substrate, comprising: a) a plurality of memory cells each implemented by a series combination of a switching transistor and a storage capacitor, said switching transistor being formed by a field effect transistor with a first gate insulating film; b) a plurality of peripheral units provided in association with said memory cells and including a first power source circuit supplied with a power voltage level for distributing the power voltage level, and a second power source circuit supplied with said power voltage level for supplying a higher voltage level than said power voltage level, one of said peripheral units being fabricated from component field effect transistors each having a second gate insulating film thinner than said first gate insulating film, a gate electrode formed on said second gate insulating film being supplied with said power voltage level; c) a plurality of word lines coupled to said memory cells, one of said word lines being coupled to a gate electrode formed on said first gate insulating film, said gate electrode on said first gate insulating film being supplied with said higher voltage level; and d) discharging means formed in said semiconductor substrate and coupled to each of said word lines through an insulating film thinner than said first gate insulating film.
Claim 3
Dependent Claim
67 words
A dynamic random access memory device as set forth in claim 1, in which said semiconductor substrate has a first conductivity type and in which each of said switching transistor and said component field effect transistor has source and drain regions of a second conductivity type opposite to said first conductivity type, wherein said discharging means are implemented by an impurity region of said second conductivity type.
Claim 4
Dependent Claim
53 words
A dynamic random access memory device as set forth in claim 1, in which said first gate insulating film ranges from about 150 angstroms to about 750 angstroms in thickness, and in which said second gate insulating film and said insulating film range from about 100 angstroms to about 250 angstroms in thickness.
Claim 5
Dependent Claim
37 words
A dynamic random access memory device as set forth in claim 1, in which said second power source circuit is implemented by a booster circuit supplied from said first power source circuit with said power voltage level.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1995-01-20 | 1995-07-22 | 1996-01-21 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1999-01-20 | 1999-07-22 | 2000-01-21 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2003-01-20 | 2003-07-22 | 2004-01-21 | $7700.00 | Window Closed / Lapsed |