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US5291127A Expired / Lapsed US ⏱️ 0.0 years remaining

Chip-lifetime testing instrument for semiconductor devices

Assignee: Samsung Electronics Co Ltd
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Filing: 1991-10-17
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Granted: 1994-03-01
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Expires: 2011-10-17
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Abstract

Abstract A chip-lifetime testing instrument for semiconductor devices which can detect defective chips by testing the performance and electrical lifetime of the chips in manufacturing process of the semiconductor devices, so that the manufacturing cost can be reduced and unnecessary processes for packaging of defective chips can be avoided, thereby reducing the necessary space for the set-up of the testing instrument.

Inventors

  • 👤 Khee Park
  • 👤 Jin H. Yoon
  • 👤 Oh S. Kwon
  • 👤 Gi Y. Jeon

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-11-07 10:50
CPC Classifications
G; G01; G01R; G01R31/00; G01R31/26; G01R31/2642; G01R31/28; G01R31/2851; G01R31/2855; G01R31/286; G01R31/2863; G01R31/2601

Claims Analysis

Total Claims: 8
Claim 1
Independent Claim 166 words
An instrument for testing chips of semiconductor devices, comprising: a tray having a slot to hold a chip to be tested, said chip having an arrangement of electrodes thereon; a plurality of probes for contacting the electrodes on said chip; a substrate to which said probes are connected, said substrate having circuit patterns connected to said probes for electrical testing of said chip; said substrate being substantially flat and said probes projecting from said substrate substantially in the plane of said substrate, said probes having ends for contacting the electrodes; said substrate being selectively mountable on said tray for bringing said ends of the probes into contact with said electrodes; marking means on the chip and the substrate for indicating angular corresponding of the substrate and the chip and consequent correspondence of the probes and the electrodes; and means on said substrate for engaging said tray to align and fix the ends of said probes and said electrodes when the substrate is mounted on said tray.
Claim 2
Dependent Claim 166 words
An instrument for testing chips of semiconductor devices, comprising: a tray having a slot to hold a chip to be tested, said chip having an arrangement of electrodes thereon; a plurality of probes for contacting the electrodes on said chip; a substrate to which said probes are connected, said substrate having circuit patterns connected to said probes for electrical testing of said chip; said substrate being substantially flat and said probes projecting from said substrate substantially in the plane of said substrate, said probes having ends for contacting the electrodes; said substrate being selectively mountable on said tray for bringing said ends of the probes into contact with said electrodes; marking means on the chip and the substrate for indicating angular corresponding of the substrate and the chip and consequent correspondence of the probes and the electrodes; and means on said substrate for engaging said tray to align and fix the ends of said probes and said electrodes when the substrate is mounted on said tray.
Claim 3
Dependent Claim 22 words
The instrument according to claim 1, wherein said ends of the probes include downwardly bent portion with tips for contacting said electrodes.
Claim 4
Dependent Claim 24 words
The instrument according to claim 1, wherein said chips and said substrate have respective corners at both of which said marking means are placed.
Claim 5
Dependent Claim 16 words
The instrument according to claim 1, wherein said substrate includes a viewing window covering said probes.
Claim 6
Dependent Claim 18 words
The instrument according to claim 4, wherein said marking means are on both said chip and said window.
Claim 7
Dependent Claim 14 words
The instrument according to claim 1, wherein said slot is recessed in said tray.
Claim 8
Dependent Claim 41 words
The instrument according to claim 6, wherein said means on said substrate for engaging said tray includes a step around said slot and a clamp secured to said substrate and engaging in said slot upon mounting the substrate on the tray.

References Cited (Backward Citations)

US3702439A Cited
US4161692A Cited
US4677474A Cited
JPS62293629A Cited
US4943767A Cited
US4820975A Cited
US4870355A Cited
US5055778A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1997-02-28 1997-08-30 1998-03-01 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 2001-02-28 2001-08-30 2002-03-01 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2005-02-28 2005-08-30 2006-03-01 $7700.00 Window Closed / Lapsed

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