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US5291071A Expired / Lapsed US ⏱️ 0.0 years remaining

High speed, low power output circuit with temperature compensated noise control

Assignee: Intel Corp
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Filing: 1992-05-12
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Granted: 1994-03-01
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Expires: 2012-05-12
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Abstract

Abstract The present invention discloses a semiconductor output circuit with temperature compensated noise control. The output circuit of the present invention presents an increase in speed, a reduction in power consumption, and a reduction in noise level as compared with the prior art temperature compensated noise control output circuits. These advantages are obtained by utilizing the present invention's current control means which current control means is driven by a temperature compensation circuit.

Inventors

  • 👤 Michael J. Allen
  • 👤 Terry L. Baucom

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-26 23:06
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/02; H03K19/173; H03K19/1733; H03K19/1735; H03K19/1736; H03K19/1731; H03K19/1737

Claims Analysis

Total Claims: 20
Claim 1
Independent Claim 516 words
A semiconductor circuit comprising: an output, a first transistor means for driving said output, a second transistor means for driving said first transistor means, a generator for generating a reference voltage electrically connected to said second transistor means, an input for receiving electrical signals and for driving said second transistor means; said first transistor means including a first driver transistor for driving said output to the supply voltage, and a second driver transistor for driving said output to ground; said transistor means including a first pre-driver circuit for driving said first driver transistor, and a second pre-driver circuit for driving said second driver transistor; said first pre-driver circuit including a first current control transistor and a first inverter, said first current control transistor being connected in series between said first inverter and the supply voltage; said input driving said first inverter; said reference voltage driving said first current control transistor so as to vary the resistivity of said first current control transistor in response to variations in said reference voltage, so as to cause said first current control transistor to vary the switching time of said first inverter in response to variations in said reference voltage; said second pre-driver circuit including a second current control transistor and a second inverter, said second current control transistor being connected in series between said second inverter and the supply voltage; said input driving said second inverter; said reference voltage driving said second current control transistor so as to vary the resistivity of said second current control transistor in response to variations in said reference voltage so as to cause said second current control transistor to vary the switching time of said second inverter in response to variations in said reference voltage; said generator generating said reference voltage by means of a temperature compensation circuit, said temperature compensation circuit causing said reference voltage to vary in response to variations of the ambient temperature; said temperature compensation circuit includes a reference current generation branch and a reference voltage generation branch; said reference current generation branch includes a resistor connecting the supply voltage and the drain of a first pull-down transistor, said first pull-down transistor having its source connected to ground, the gate of said first pull-down transistor being connected to a voltage above the threshold voltage of said first pull-down transistor, said reference voltage generation branch includes a second pull-down transistor, said gate of said second pull-down transistor being driven by said drain of said first pull-down transistor, said source of said pull-down transistor being connected to ground, said drain of said second pull-down transistor being connected to the drain of a pull-up transistor, the source of said pull-up transistor being connected to the supply voltage, the gate of said pull-up transistor being connected to said drain of said pull-up transistor; said drain of said pull-up transistor generating said reference voltage; and said output varying in response to corresponding variations of said input, and said output switching time varying in response to variations in said switching time of said first and said second inverters of said first and second respective pre-drivers.
Claim 2
Dependent Claim 516 words
A semiconductor circuit comprising: an output, a first transistor means for driving said output, a second transistor means for driving said first transistor means, a generator for generating a reference voltage electrically connected to said second transistor means, an input for receiving electrical signals and for driving said second transistor means; said first transistor means including a first driver transistor for driving said output to the supply voltage, and a second driver transistor for driving said output to ground; said transistor means including a first pre-driver circuit for driving said first driver transistor, and a second pre-driver circuit for driving said second driver transistor; said first pre-driver circuit including a first current control transistor and a first inverter, said first current control transistor being connected in series between said first inverter and the supply voltage; said input driving said first inverter; said reference voltage driving said first current control transistor so as to vary the resistivity of said first current control transistor in response to variations in said reference voltage, so as to cause said first current control transistor to vary the switching time of said first inverter in response to variations in said reference voltage; said second pre-driver circuit including a second current control transistor and a second inverter, said second current control transistor being connected in series between said second inverter and the supply voltage; said input driving said second inverter; said reference voltage driving said second current control transistor so as to vary the resistivity of said second current control transistor in response to variations in said reference voltage so as to cause said second current control transistor to vary the switching time of said second inverter in response to variations in said reference voltage; said generator generating said reference voltage by means of a temperature compensation circuit, said temperature compensation circuit causing said reference voltage to vary in response to variations of the ambient temperature; said temperature compensation circuit includes a reference current generation branch and a reference voltage generation branch; said reference current generation branch includes a resistor connecting the supply voltage and the drain of a first pull-down transistor, said first pull-down transistor having its source connected to ground, the gate of said first pull-down transistor being connected to a voltage above the threshold voltage of said first pull-down transistor, said reference voltage generation branch includes a second pull-down transistor, said gate of said second pull-down transistor being driven by said drain of said first pull-down transistor, said source of said pull-down transistor being connected to ground, said drain of said second pull-down transistor being connected to the drain of a pull-up transistor, the source of said pull-up transistor being connected to the supply voltage, the gate of said pull-up transistor being connected to said drain of said pull-up transistor; said drain of said pull-up transistor generating said reference voltage; and said output varying in response to corresponding variations of said input, and said output switching time varying in response to variations in said switching time of said first and said second inverters of said first and second respective pre-drivers.
Claim 3
Dependent Claim 20 words
The semiconductor circuit of claim 1 wherein said first driver transistor of said first transistor means is an N-channel transistor.
Claim 4
Dependent Claim 20 words
The semiconductor circuit of claim 1 wherein said second driver transistor of said first transistor means is an N-channel transistor.
Claim 5
Dependent Claim 21 words
The semiconductor circuit of claim 1 wherein said first current control transistor of said first pre-driver circuit is a P-channel transistor.
Claim 6
Dependent Claim 21 words
The semiconductor circuit of claim 1 wherein said second current control transistor of said second pre-driver circuit is a P-channel transistor.
Claim 7
Dependent Claim 56 words
The semiconductor circuit of claim 1 wherein said reference voltage causes the resistivity of said first and said second current control transistors to vary in response to variations in said reference voltage so as to cause said switching times of said first and said second inverters to vary in response to variations in said reference voltage.
Claim 8
Dependent Claim 58 words
The semiconductor circuit of claim 6 wherein said reference voltage causes the switching times of said first inverter and said second inverters to decrease in response to an increase in said reference voltage, said reference voltage causes the switching times of said first and said second inverters to increase in response to a decrease in said reference voltage.
Claim 9
Dependent Claim 37 words
The semiconductor circuit of claim 1 wherein said temperature compensation circuit lowers said reference voltage in response to a rising ambient temperature, said temperature compensation circuit increases said reference voltage in response to a falling ambient temperature.
Claim 10
Dependent Claim 17 words
The semiconductor circuit of claim 1 wherein said semiconductor circuit is fabricated on a P-type silicon substrate.
Claim 11
Dependent Claim 503 words
A semiconductor circuit comprising: an output, a first transistor means for driving said output, a second transistor means for driving said first transistor means, a reference voltage electrically connected to said second transistor means, a temperature compensation circuitry for generating said reference voltage, an input for receiving electrical signals and for driving said second transistor means; said temperature compensation circuitry causing said reference voltage to vary in response to variations in the ambient temperature; said temperature compensation circuit includes a reference current generation branch and a reference voltage generation branch; said reference current generation branch includes a resistor connecting the supply voltage and the drain of a first pull-down transistor, said first pull-down transistor having its source connected to ground, the gate of said first pull-down transistor being connected to a voltage above the threshold voltage of said first pull-down transistor; said reference voltage generation branch includes a second pull-down transistor, said gate of said second pull-down transistor being driven by said drain of said first pull-down transistor, said source of said pull-down transistor being connected to ground, said drain of said second pull-down transistor being connected to the drain of a pull-up transistor, the source of said pull-up transistor being connected to the supply voltage, the gate of said pull-up transistor being connected to said drain of said pull-up transistor; said drain of said pull-up transistor generating said reference voltage; said first transistor means including a first driver transistor for driving said output to the supply voltage, and a second driver transistor for driving said output to ground; said second transistor means including a first pre-driver circuit for driving said first driver transistor, and a second pre-driver circuit for driving said second driver transistor; said first pre-driver circuit including a first current control transistor and a first inverter, said first current control transistor being connected in series between said first inverter and the supply voltage; said input driving said first inverter; said reference voltage driving said first current control transistor so as to vary the resistivity of said first current control transistor in response to variations in the ambient temperature; said first current control transistor causing the switching time of said first inverter to vary in response to variations in the ambient temperature; said second pre-driver circuit includes a second current control transistor and a second inverter, said second current control transistor being connected in series between said second inverter and the supply voltage; said input driving said second inverter; said reference voltage driving said second current control transistor so as to vary the resistivity of said second current control transistor in response to variations in the ambient temperature; said second current control transistor causing the switching time of said second inverter to vary in response to variations in the ambient temperature; and said output varying in response to corresponding variations of said input, and said output switching time varying in response to variations in said switching time of said first and said second inverters of said first and second respective pre-drivers.
Claim 12
Dependent Claim 503 words
A semiconductor circuit comprising: an output, a first transistor means for driving said output, a second transistor means for driving said first transistor means, a reference voltage electrically connected to said second transistor means, a temperature compensation circuitry for generating said reference voltage, an input for receiving electrical signals and for driving said second transistor means; said temperature compensation circuitry causing said reference voltage to vary in response to variations in the ambient temperature; said temperature compensation circuit includes a reference current generation branch and a reference voltage generation branch; said reference current generation branch includes a resistor connecting the supply voltage and the drain of a first pull-down transistor, said first pull-down transistor having its source connected to ground, the gate of said first pull-down transistor being connected to a voltage above the threshold voltage of said first pull-down transistor; said reference voltage generation branch includes a second pull-down transistor, said gate of said second pull-down transistor being driven by said drain of said first pull-down transistor, said source of said pull-down transistor being connected to ground, said drain of said second pull-down transistor being connected to the drain of a pull-up transistor, the source of said pull-up transistor being connected to the supply voltage, the gate of said pull-up transistor being connected to said drain of said pull-up transistor; said drain of said pull-up transistor generating said reference voltage; said first transistor means including a first driver transistor for driving said output to the supply voltage, and a second driver transistor for driving said output to ground; said second transistor means including a first pre-driver circuit for driving said first driver transistor, and a second pre-driver circuit for driving said second driver transistor; said first pre-driver circuit including a first current control transistor and a first inverter, said first current control transistor being connected in series between said first inverter and the supply voltage; said input driving said first inverter; said reference voltage driving said first current control transistor so as to vary the resistivity of said first current control transistor in response to variations in the ambient temperature; said first current control transistor causing the switching time of said first inverter to vary in response to variations in the ambient temperature; said second pre-driver circuit includes a second current control transistor and a second inverter, said second current control transistor being connected in series between said second inverter and the supply voltage; said input driving said second inverter; said reference voltage driving said second current control transistor so as to vary the resistivity of said second current control transistor in response to variations in the ambient temperature; said second current control transistor causing the switching time of said second inverter to vary in response to variations in the ambient temperature; and said output varying in response to corresponding variations of said input, and said output switching time varying in response to variations in said switching time of said first and said second inverters of said first and second respective pre-drivers.
Claim 13
Dependent Claim 20 words
The semiconductor circuit of claim 10 wherein said first driver transistor of said first transistor means is an N-channel transistor.
Claim 14
Dependent Claim 20 words
The semiconductor circuit of claim 10 wherein said second driver transistor of said first transistor means is an N-channel transistor.
Claim 15
Dependent Claim 21 words
The semiconductor circuit of claim 10 wherein said first current control transistor of said first pre-driver circuit is a P-channel transistor.
Claim 16
Dependent Claim 21 words
The semiconductor circuit of claim 10 wherein said second current control transistor of said second pre-driver circuit is a P-channel transistor.
Claim 17
Dependent Claim 54 words
The semiconductor circuit of claim 10 wherein said reference voltage causes the resistivity of said first and said second current control transistors to vary in response to variations in said reference voltage thereby causing said switching times of said first and said second inverters to vary in response to variations in said reference voltage.
Claim 18
Dependent Claim 59 words
The semiconductor circuit of claim 15 wherein said reference voltage causes the switching times of said first inverter and said second inverters to decrease in response to an increase in said reference voltage, said reference voltage further causes the switching times of said first and said second inverters to increase in response to a decrease in said reference voltage.
Claim 19
Dependent Claim 37 words
The semiconductor circuit of claim 10 wherein said temperature compensation circuit lowers said reference voltage in response to a rising ambient temperature, said temperature compensation circuit increases said reference voltage in response to a falling ambient temperature.
Claim 20
Dependent Claim 17 words
The semiconductor circuit of claim 10 wherein said semiconductor circuit is fabricated on a P-type silicon substrate.

References Cited (Backward Citations)

US4894561A Cited
US4975598A Cited
US4975599A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1997-02-28 1997-08-30 1998-03-01 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 2001-02-28 2001-08-30 2002-03-01 $3760.00 Window Closed / Lapsed
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