Patent US5290727A successfully refreshed from Google Patents.
US5290727A
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Method for suppressing charge loss in EEPROMs/EPROMS and instabilities in SRAM load resistors
Assignee: LSI Corp
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Filing: 1992-03-30
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Granted: 1994-03-01
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Expires: 2012-03-30
Abstract
Abstract Suppression of charge loss and hot carrier degradation in EEPROMs and EPROMs, and of instability in the polysilicon pull-up resistors associated with SRAMs is achieved by the inclusion of at least one layer of silicon-enriched oxide in the MOS structure. In such MOS structures, the silicon-enriched oxide layer may be disposed immediately beneath the interlayer dielectric layer, or immediately beneath the inter-metal oxide layer, or immediately beneath the passivation layer, or in any combination of these locations. Each silicon-enriched oxide layer preferably contains at least about 10 17 per cm 3 dangling bonds.
Inventors
- 👤 Vivek Jain
- 👤 Dipankar Pramanik
- 👤 Subhash Nariani
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-05 04:18
CPC Classifications
H; H10; H10P; H10P14/00; H10P14/60; H10P14/66; H10P14/668; H10P14/6681; H10P14/6682; H10B; H10B10/00; H10B69/00; H10P14/63; H10P14/6326; H10P14/6328; H10P14/6334; H10P14/6336; H10W; H10W20/00; H10W20/40; H10W20/45; H10W20/48; H10W74/00; H10W74/40; H10W74/43; H10W74/481; H10P14/69; H10P14/692; H10P14/6921; H10P14/69215
Claims Analysis
Total Claims: 18
Claim 1
Independent Claim
87 words
A method of making an integrated circuit MOS device having improved reliability, the method comprising: (a) forming on a substrate a plurality of MOS active devices, each including at least one gate; (b) forming a first layer of silicon-enriched oxide generally above a level of said substrate defined by said MOS active devices, said silicon-enriched oxide having a refractive index of at least 1.50 and having a layer thickness less than about 5,000 Å; wherein said first layer of silicon-enriched oxide improves operation of said MOS devices.
Claim 2
Independent Claim
87 words
A method of making an integrated circuit MOS device having improved reliability, the method comprising: (a) forming on a substrate a plurality of MOS active devices, each including at least one gate; (b) forming a first layer of silicon-enriched oxide generally above a level of said substrate defined by said MOS active devices, said silicon-enriched oxide having a refractive index of at least 1.50 and having a layer thickness less than about 5,000 Å; wherein said first layer of silicon-enriched oxide improves operation of said MOS devices.
Claim 3
Dependent Claim
60 words
The method of claim 1, wherein at least one said MOS active device includes a first gate formed at a first gate level and a second gate formed at an overlying second gate level, said first gate adapted to store charge representing a stored data value; wherein said first layer of silicon-enriched oxide improves charge retention of said first gate.
Claim 4
Dependent Claim
23 words
The method of claim 1, wherein said first layer of silicon-enhanced oxide contains at least about 10 17 per cm 3 dangling bonds.
Claim 5
Dependent Claim
23 words
The method of claim 1, wherein said first layer of silicon-enriched oxide has a thickness of about 1,000 Å to about 5,000 Å.
Claim 6
Dependent Claim
60 words
The method of claim 1, including the further steps of: (c) providing an interlayer dielectric disposed generally above a level defined by said MOS active devices; and (d) providing a first pattern of metal traces at a first trace level generally overlying said interlayer dielectric; wherein said first layer of silicon-enriched oxide is disposed at immediately beneath said interlayer dielectric.
Claim 7
Dependent Claim
62 words
The method of claim 1, including the further steps of: (c) providing an interlayer dielectric disposed generally above a level defined by said MOS active devices; and (d) providing a first pattern of metal traces at a first trace level generally overlying said interlayer dielectric; wherein said first layer of silicon-enriched oxide is disposed above said interlayer dielectric and first trace level.
Claim 8
Dependent Claim
40 words
The method of claim 1, including the further step of forming a passivation layer generally above a level defined by said MOS active devices; wherein said first layer of silicon-enriched oxide is disposed adjacent and immediately beneath said passivation layer.
Claim 9
Dependent Claim
58 words
The method of claim 1, including the further step of forming a polysilicon resistor at a level substantially equal to a gate level of at least one said MOS device, said polysilicon resistor having a first end coupled to said at least one MOS device; wherein said first layer of silicon-enriched oxide preserves stability of said polysilicon resistor.
Claim 10
Dependent Claim
60 words
The method of claim 8, including the further steps of: (c) providing an interlayer dielectric disposed generally above a level defined by said MOS active devices; and (d) providing a first pattern of metal traces at a first trace level generally overlying said interlayer dielectric; wherein said first layer of silicon-enriched oxide is disposed at immediately beneath said interlayer dielectric.
Claim 11
Dependent Claim
62 words
The method of claim 8, including the further steps of: (c) providing an interlayer dielectric disposed generally above a level defined by said MOS active devices; and (d) providing a first pattern of metal traces at a first trace level generally overlying said interlayer dielectric; wherein said first layer of silicon-enriched oxide is disposed above said interlayer dielectric and first trace level.
Claim 12
Dependent Claim
40 words
The method of claim 8, including the further step of forming a passivation layer generally above a level defined by said MOS active devices; wherein said first layer of silicon-enriched oxide is disposed adjacent and immediately beneath said passivation layer.
Claim 13
Dependent Claim
18 words
The method of claim 1, wherein step (b) is carried out at a temperature of about 400° C.
Claim 14
Dependent Claim
18 words
The method of claim 1, wherein step (b) is carried out using plasma enhanced chemical vapor deposition ("PECVD").
Claim 15
Dependent Claim
17 words
The method of claim 1, wherein step (b) is carried out using silane, nitrous oxide and nitrogen.
Claim 16
Dependent Claim
19 words
The method of claim 1, wherein said plurality of MOS active devices includes a plurality of MOS memory devices.
Claim 17
Dependent Claim
23 words
The method of claim 15, wherein said first layer of silicon-enriched oxide contains at least about 10 17 per cm 3 dangling bonds.
Claim 18
Dependent Claim
18 words
The method of claim 15, wherein step (b) is carried out at a temperature of about 400° C.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
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| 3.5 Years (Year 4) | 1997-02-28 | 1997-08-30 | 1998-03-01 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-02-28 | 2001-08-30 | 2002-03-01 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-02-28 | 2005-08-30 | 2006-03-01 | $7700.00 | Window Closed / Lapsed |