Patent US5290720A successfully refreshed from Google Patents.
US5290720A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Transistor with inverse silicide T-gate structure
Assignee: Nokia Bell Labs
•
Filing: 1993-07-26
•
Granted: 1994-03-01
•
Expires: 2013-07-26
Abstract
Abstract A method of making a silicided inverse T-gate with an L-shaped silicon spacer and nitride sidewall spacers is described. The L-shaped spacer is electrically connected to the gate.
Inventors
- 👤 Min-Liang Chen
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 07:51
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/01; H10D30/021; H10D30/0223; H10D30/0227; H10D30/0229; H10D64/00; H10D64/20; H10D64/27; H10D64/311; H10D64/411; H10D64/511; H10D64/517; H10D64/518; H10D84/00; H10D84/01; H10D84/0123; H10D84/0126; H10D84/0165; H10D84/0172; H10D84/0174; H10D84/02; H10D84/03; H10D84/038; H10D84/80; H10D84/82; H10D84/83; H10D84/85; H10D84/859
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
139 words
A method of making a semiconductor device comprising the steps of forming a gate structure comprising a thin oxide and polysilicon layer, said thin oxide being between said substrate and said polysilicon and on the surfaces of polysilicon; forming source/drain regions on opposed sides of said gate structure, said forming being by ion implantation to form lightly and heavily doped regions, said implantation being a single implant through L-shaped silicon spacers and forming said lightly doped regions under said spacers; said gate structure being an inverse T-gate being made by the further steps of forming said L-shaped silicon spacers on opposed sides of said gate structure by depositing a silicon layer and then a sacrificial layer over said thin oxide and polysilicon layers, and selectively removing said silicon layer and said sacrificial layer to form said L-shaped silicon spacer.
Claim 2
Independent Claim
139 words
A method of making a semiconductor device comprising the steps of forming a gate structure comprising a thin oxide and polysilicon layer, said thin oxide being between said substrate and said polysilicon and on the surfaces of polysilicon; forming source/drain regions on opposed sides of said gate structure, said forming being by ion implantation to form lightly and heavily doped regions, said implantation being a single implant through L-shaped silicon spacers and forming said lightly doped regions under said spacers; said gate structure being an inverse T-gate being made by the further steps of forming said L-shaped silicon spacers on opposed sides of said gate structure by depositing a silicon layer and then a sacrificial layer over said thin oxide and polysilicon layers, and selectively removing said silicon layer and said sacrificial layer to form said L-shaped silicon spacer.
Claim 3
Dependent Claim
31 words
A method as recited in claim 1 comprising the further step of removing the thin oxide from the polysilicon on the top of the gate structure and from the source/drain regions.
Claim 4
Dependent Claim
34 words
A method as recited in claim 2 comprising the further step of siliciding the top of said gate structure and said source/drain regions, said siliciding step electrically connecting said gate and said L-shaped spacer.
Claim 5
Dependent Claim
20 words
A method as recited in claim 3 comprising the further step of forming dielectric sidewall spacers on said L-shaped spacer.
Claim 6
Dependent Claim
14 words
A method as recited in claim 4 in which said dielectric comprises silicon nitride.
Claim 7
Independent Claim
137 words
A method of making a semiconductor device comprising the steps of forming a gate structure comprising a thin oxide and polysilicon layer, said thin oxide being between said substrate and said polysilicon and on the surfaces of polysilicon; said gate structure being an inverse T-gate being made by the steps of forming conductive spacers on opposed sides of said gate structure by depositing a silicon layer and then a sacrificial layer over said thin oxide and polysilicon layers, and selectively removing said silicon layer and said sacrificial layer to form said conductive silicon spacer; and forming source/drain regions on opposed sides of said gate structure, said forming being by ion implantation to form lightly and heavily doped regions, said implantation being a single implant through conductive silicon spacers and forming said lightly doped regions under said spacers.
Claim 8
Independent Claim
137 words
A method of making a semiconductor device comprising the steps of forming a gate structure comprising a thin oxide and polysilicon layer, said thin oxide being between said substrate and said polysilicon and on the surfaces of polysilicon; said gate structure being an inverse T-gate being made by the steps of forming conductive spacers on opposed sides of said gate structure by depositing a silicon layer and then a sacrificial layer over said thin oxide and polysilicon layers, and selectively removing said silicon layer and said sacrificial layer to form said conductive silicon spacer; and forming source/drain regions on opposed sides of said gate structure, said forming being by ion implantation to form lightly and heavily doped regions, said implantation being a single implant through conductive silicon spacers and forming said lightly doped regions under said spacers.
Claim 9
Dependent Claim
31 words
A method as recited in claim 6 comprising the further step of removing the thin oxide from the polysilicon on the top of the gate structure and from the source/drain regions.
Claim 10
Dependent Claim
34 words
A method as recited in claim 7 comprising the further step of siliciding the top of said gate structure and said source/drain regions, said siliciding step electrically connecting said gate and said L-shaped spacer.
Claim 11
Dependent Claim
20 words
A method as recited in claim 8 comprising the further step of forming dielectric sidewall spacers on said L-shaped spacer.
Claim 12
Dependent Claim
14 words
A method as recited in claim 9 in which said dielectric comprises silicon nitride.
References Cited (Backward Citations)
US4868617A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1997-02-28 | 1997-08-30 | 1998-03-01 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-02-28 | 2001-08-30 | 2002-03-01 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-02-28 | 2005-08-30 | 2006-03-01 | $7700.00 | Window Closed / Lapsed |