Clock information transmitting device and clock information receiving device

Claim 1

A clock information transmitting device coupled to a digital processing circuit which receives a transmission signal and generates a coded transmission signal, comprising: signal separation means for separating a synchronizing signal from the transmission signal; phase locked loop (PLL) means, coupled to said signal separation means, for generating a sampling clock signal and a first signal produced from said sampling clock signal, said sampling clock signal and said first signal being synchronized with the synchronizing signal, the sampling clock signal generated in the PLL mans being applied to and used in the digital processing circuit; clock information generating means for generating a transmission clock signal and being coupled to said PLL means, for counting pulses of the transmission clock signal and for generating clock information indicating a number of pulses of the transmission clock signal in response to the first signal generated by the PLL means; and multiplexer means, coupled to said digital processing circuit and said clock information generating means, for outputting a multiplexed signal including said clock information and said coded transmission signal to a transmission path, wherein said clock information generating means comprises: clock signal generating means for generating the transmission clock signal and a second signal having a frequency lower than that of the transmission clock signal, the multiplexed signal having a frequency equal to that of the transmission clock signal; counter means, coupled to said clock signal generating means, for counting pulses of the transmission clock signal during each period defined by said second signal; and latch means, coupled to said PLL means and said counter means, for latching a counter value in the counter means in response to the first signal generated by said PLL means, said counter value corresponding to said clock information.