US4853781A
Expired / Lapsed
US
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Video format signal processing system
Assignee: Pioneer Corp
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Filing: 1988-03-10
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Granted: 1989-08-01
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Expires: 2008-03-10
Abstract
Abstract A video processing system in which data obtained from sampling an input video format signal according to a first timing signal is written into a first memory according to the first timing signal. Data is read-out of the first memory according to a second timing signal having a frequency equal to N times that of a horizontal synchronizing frequency of the input signal, thereby obtaining data with no time-base fluctuation. M-samples of data from the first memory is then written into a second memory, and data from the second memory is read-out such that the read-out signal from the second memory has a different phase than that of the input video format signal. The system is operable for simultaneously stopping data being read-out of the first memory and data being written into the second memory for a period of time equal to R+kM samples of the input video format signal, wherein R is an integer remainder of N/M, and k is either a positive integer or zero.
Inventors
- 👤 Takashi Okano
- 👤 Toru Akiyama
- 👤 Masao Kanda
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 07:06
CPC Classifications
H; H04; H04N; H04N5/00; H04N5/76; H04N5/91; H04N5/93; H04N5/95; H04N5/956
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
305 words
A system for processing an input video format signal having a time-base fluctuation and having a horizontal synchronizing signal portion, comprising: means for synchronizing a first timing signal with the time-base fluctuation of the input video format signal; means for sampling the input video format signal according to said synchronized first timing signal; first and second memory means; means for writing the sampled input video format signal into said first memory means according to said synchronized first timing signal so that the written sampled input video format signal has no time-base fluctuation; means for reading-out data from said first memory means according to a second timing signal, said second timing signal having a frequency equal to N times a frequency of the horizontal synchronizing signal of the input video format signal; means for writing M samples of data read-out from said first memory means into said second memory means; means for reading-out data from said second memory means such that an output video format signal read-out from said second memory means has a phase which is different from that of the input video format signal; and means for activating said means for reading-out data from said first memory means and said means for reading-out data from said second memory means; and means for simultaneously inhibiting both said means for reading-out data from said first memory means and said means for writing data into said second memory means, said inhibiting means being activated within at least one horizontal scanning period after said means for reading-out data from said second memory means is activated, and said inhibiting means being activated for a period of time equal to R+kM samples of the input format video signal, wherein R is an integer remainder of N divided by M, and wherein k is one of a positive integer and zero.
Claim 2
Independent Claim
305 words
A system for processing an input video format signal having a time-base fluctuation and having a horizontal synchronizing signal portion, comprising: means for synchronizing a first timing signal with the time-base fluctuation of the input video format signal; means for sampling the input video format signal according to said synchronized first timing signal; first and second memory means; means for writing the sampled input video format signal into said first memory means according to said synchronized first timing signal so that the written sampled input video format signal has no time-base fluctuation; means for reading-out data from said first memory means according to a second timing signal, said second timing signal having a frequency equal to N times a frequency of the horizontal synchronizing signal of the input video format signal; means for writing M samples of data read-out from said first memory means into said second memory means; means for reading-out data from said second memory means such that an output video format signal read-out from said second memory means has a phase which is different from that of the input video format signal; and means for activating said means for reading-out data from said first memory means and said means for reading-out data from said second memory means; and means for simultaneously inhibiting both said means for reading-out data from said first memory means and said means for writing data into said second memory means, said inhibiting means being activated within at least one horizontal scanning period after said means for reading-out data from said second memory means is activated, and said inhibiting means being activated for a period of time equal to R+kM samples of the input format video signal, wherein R is an integer remainder of N divided by M, and wherein k is one of a positive integer and zero.
Claim 3
Dependent Claim
37 words
The system according to claim 1, wherein said synchronizing means comprises: a synchronization separator circuit for separating the horizontal synchronizing signal from the input video signal: and a time-base control circuit connected to said synchronization separator circuit.
Claim 4
Dependent Claim
44 words
The system according to claim 1, further comprising serial-to-parallel converter means coupled between said first and second memory means; and means for receiving parallel data from said second memory means and for converting the parallel data from said second memory means into serial data.
Claim 5
Dependent Claim
35 words
The system according to claim 1, further comprising: an oscillator for generating a clock signal having a frequency equal to N times the frequency of the horizontal synchronizing signal of the input video format signal.
Claim 6
Dependent Claim
34 words
The system according to claim 1, wherein said means for writing data into said second memory means and said means for reading-out data from said second memory means are selectively by said activating means.
Claim 7
Dependent Claim
41 words
The system according to claim 2, wherein said time-base control circuit comprises, a divider circuit, a voltage-controlled oscillator connected to said divider circuit, and a phase comparator for receiving said separated horizontal synchronizing signal and an output of said divider circuit.
Claim 8
Dependent Claim
53 words
The system according to claim 3, further comprising, an analog-to-digital means for receiving the input video format signal and for supplying a digitized input video format signal to said first memory means, and digital-to-analog converter means for receiving parallel data from said second memory means and for supplying the output video format signal.
Claim 9
Dependent Claim
37 words
The system according to claim 4, further comprising counter means for counting a predetermined number of pulses of said clock signal, and for activating said inhibiting means in response to the predetermined number of clock signal pulses.
Claim 10
Dependent Claim
27 words
The system according to claim 4, further comprising means for dividing said clock signal by N, thereby producing a read-out starting pulse for said second memory means.
Claim 11
Dependent Claim
26 words
The system according to claim 4, further comprising means for dividing said clock signal by M, thereby producing a read-out clock for said second memory means.
Claim 12
Dependent Claim
54 words
The system according to claim 10, further comprising counter means for counting a predetermined number of pulses of said clock signal, and for activating said inhibiting means in response to the predetermined number of clock signal pulses, wherein said counter means is reset in response to said read-out clock for said second memory means.
Claim 13
Dependent Claim
52 words
The system according to claim 10, further comprising dividing means coupled to said means for dividing said clock signal by M and to said first and second memory means, said dividing means supplies a read-out starting pulse to said first memory means, and a writing start pulse to said second memory means.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1992-07-31 | 1993-01-30 | 1993-08-01 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1996-07-31 | 1997-01-30 | 1997-08-01 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2000-07-31 | 2001-01-30 | 2001-08-01 | $7700.00 | Window Closed / Lapsed |