Line-locked digital fluorography system

Claim 1

In a digital fluorography system including a television (TV) camera whose target is scanned to convert x-ray image frames to corresponding analog video signals, a analog-to-digital converter (ADC) for converting successive samples of the analog signals in the horizontal scan lines to digital pixel words having values corresponding to the intensities of the picture elements (pixels) that compose the lines of the frames, a sync generator for providing the timing signals including the vertical and horizontal sync signals, for the TV camera and the sample clock signals for determining the sampling frequency of the ADC, digital video processor (DVP) means including means for subtracting an image frame from any image frame in sequence of frames to produce a sequence of difference images, means providing timing signals for the DVP including vertical and horizontal sync signals and sample clock signals that may differ slightly in phase and frequency or both from corresponding signals for the TV camera and the ADC, and, a first-in, first-out (FIFO) buffer system interposed between the ADC and the DVP to compensate for said timing difference, comprising: a serial-to-parallel converter for converting each predetermined number of serial pixel words that are output from said ADC to a parallel word, producing a second clock pulse frequency for said converter by dividing the ADC sample clock frequency by a number equal to the number of pixel words that are combined at a time by said converter to produce said parallel words, pre-FIFO memory means for being loaded with successive parallel words from said serial-to-parallel converter in response to occurrence of clock pulses at said second frequency, means for dividing said sample clock signals for said DVP by the number corresponding to the number of pixel words that are parallel to produce clocking signals for controlling said pre-FIFO memory to output said parallel words in first-in, first-out order, random-access memory (RAM) means having input means or said output parallel words from said pre-FIFO and having output means, said RAM means being divided into a plurality of horizontal line segments each of which has a series of locations for the respective parallel words that compose a horizontal television line, means responding to occurrence of the respective horizontal sync pulses that follow a frame initiating vertical sync pulse by addressing the parallel words from said pre-FIFO that make up the current horizontal line to be written in said horizontal line segments in succession and then recycling said addresses each time the last segment is filled, means responsive to occurrence of the respective horizontal sync pulses that follow a frame initiating vertical sync pulse and a delay period by addressing the first line segment to read out it and following line segments in succession and then recycling said addresses each time the last segment is read out, and a parallel-to-serial converter operative to convert the successive parallel words read out from said RAM locations to serial pixel words again.