US5289284A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Video processing circuit with line memory control
Assignee: Technicolor USA Inc
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Filing: 1991-05-30
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Granted: 1994-02-22
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Expires: 2011-05-30
Abstract
Abstract A line memory and control system comprises a line memory, for example a first in first out (FIFO) device. A comparator compares a first value, specifying a location in the horizontal line period where reading or writing of the line memory is to begin, with a second value, fixing pixel location within each line period. A register stores the number of data samples stored in the line memory. A counter counts the number of data samples which have actually been written into the line memory or read from the line memory. The counter has an output of the comparator as a first input and the number of data samples previously stored in the line memory as a second input. In the case of both compression and expansion, a line memory control system assures that the number of samples written into each FIFO line memory be the same as the number of samples read out of each FIFO line memory.
Inventors
- 👤 Nathaniel H. Ersoz
- 👤 Timothy W. Saeger
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 06:13
CPC Classifications
H; H04; H04N; H04N9/00; H04N9/64; H04N9/641; G; G06; G06T; G06T3/00; G06T3/04; G06T3/40; G06T3/4007; H04N19/00; H04N19/90; H04N3/00; H04N3/10; H04N3/16; H04N3/22; H04N3/223; H04N3/227; H04N3/27; H04N5/00; H04N5/222; H04N5/262; H04N5/2624; H04N5/44; H04N5/445; H04N5/45; H04N7/00; H04N7/007; H04N7/01; H04N7/0105; H04N7/0117; H04N7/0122; H04N7/015
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
150 words
A video signal processing circuit, comprising: a line memory for said video signal; means for writing and reading of video data samples into and out of said line memory, different numbers of data samples per line being stored during expansion and compression of said video signal; means for comparing a first value, specifying a first pixel location in the horizontal line period where reading or writing of said line memory is to begin, with a second value specifying a second pixel location within each line period; means for storing a third value corresponding to the number of data samples stored in said line memory; and, means for counting the number of data samples which have actually been written into said line memory or read from said line memory, said counting means having an output of said comparing means as a first input and said third value as a second input.
Claim 2
Dependent Claim
150 words
A video signal processing circuit, comprising: a line memory for said video signal; means for writing and reading of video data samples into and out of said line memory, different numbers of data samples per line being stored during expansion and compression of said video signal; means for comparing a first value, specifying a first pixel location in the horizontal line period where reading or writing of said line memory is to begin, with a second value specifying a second pixel location within each line period; means for storing a third value corresponding to the number of data samples stored in said line memory; and, means for counting the number of data samples which have actually been written into said line memory or read from said line memory, said counting means having an output of said comparing means as a first input and said third value as a second input.
Claim 3
Dependent Claim
18 words
The circuit of claim 1, further comprising means for smoothing data compressed or expanded in said line memory.
Claim 4
Dependent Claim
24 words
The circuit of claim 1, wherein said line memory is a first in first out (FIFO) device having independently enabled write and read ports.
Claim 5
Dependent Claim
152 words
A controller for a line memory in a video signal processing circuit, the controller comprising: means for writing and reading of video data samples into and out of said line memory, different numbers of data samples per line being stored during expansion and compression of said video signal; means for comparing a first value, specifying a first pixel location in the horizontal line period where reading or writing of said line memory is to begin, with a second value specifying a second pixel location within each line period; means for storing a third value corresponding to the number of data samples stored in said line memory; and, means for counting the number of data samples which have actually been written into said line memory or read from said line memory, said counting means having an output of said comparing means as a first input and said third value as a second input.
Claim 6
Dependent Claim
152 words
A controller for a line memory in a video signal processing circuit, the controller comprising: means for writing and reading of video data samples into and out of said line memory, different numbers of data samples per line being stored during expansion and compression of said video signal; means for comparing a first value, specifying a first pixel location in the horizontal line period where reading or writing of said line memory is to begin, with a second value specifying a second pixel location within each line period; means for storing a third value corresponding to the number of data samples stored in said line memory; and, means for counting the number of data samples which have actually been written into said line memory or read from said line memory, said counting means having an output of said comparing means as a first input and said third value as a second input.
Claim 7
Dependent Claim
18 words
The controller of claim 4, further comprising means for smoothing data compressed or expanded in said line memory.
Claim 8
Dependent Claim
24 words
The circuit of claim 4, wherein said line memory is a first in first out (FIFO) device having independently enabled write and read ports.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1997-02-21 | 1997-08-23 | 1998-02-22 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-02-21 | 2001-08-23 | 2002-02-22 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-02-21 | 2005-08-23 | 2006-02-22 | $7700.00 | Window Closed / Lapsed |