Progressive scan television receiver with adaptive memory addressing

Claim 2

In a progressive scan video processor of the type having memory means for storing a video input signal supplied thereto during a first line interval thereof and for recovering the stored signal N-times during a subsequent line interval to provide a processed video output signal having a line rate N-times that of said video input signal, said memory means being coupled to address generator means for receiving read and write addresses therefrom, the improvement, comprising: circuit means coupled to said generator means for storing the last address written in said memory means during a memory write operation and for controlling the starting time of at least one subsequent memory read operation in accordance with the stored address.

Claim 3

A video processor as recited in claim 1 further comprising second circuit means coupled to said address generator means for initializing said address generator means to a given starting address in response to a horizontal synchronizing component of said video input signal.

Claim 4

A video processor as recited in claim 1 wherein said circuit means comprises: (a) latch means coupled to receive and store said last address written in said memory means during said memory write operation; (b) comparator means coupled to input and output means of said latch means for providing an end-of-line indicator signal; and (c) coupling means for coupling said end-of-line indicator signal to an input of said address generator means for initializing said address generator means to a given starting address in response to said end-of-line indicator signal.

Claim 5

A progressive scan video display apparatus, comprising: (a) input means for receiving a video input signal to be displayed; (b) read/write memory means coupled to said input means for storing said video input signal during a first line interval thereof and for recovering the stored signal N-times during a subsequent line interval to provide a processed video signal having a line rate N-times that of said video input signal; (c) display means having a horizontal deflection rate N-times the line rate of said video input signal and coupled to said memory means for displaying said processed video signal recovered from said memory means; (d) memory address generator means coupled to said memory means for supplying write addresses thereto during said first line interval and for supplying read addresses thereto during said subsequent line interval; and (e) circuit means coupled to said generator means for storing the last address written in said memory means during a memory write operation and for controlling the starting time of at least one subsequent memory read operation in accordance with the stored address.

Claim 6

A progressive scan video display apparatus, comprising: (a) input means for receiving a video input signal to be displayed; (b) read/write memory means coupled to said input means for storing said video input signal during a first line interval thereof and for recovering the stored signal N-times during a subsequent line interval to provide a processed video signal having a line rate N-times that of said video input signal; (c) display means having a horizontal deflection rate N-times the line rate of said video input signal and coupled to said memory means for displaying said processed video signal recovered from said memory means; (d) memory address generator means coupled to said memory means for supplying write addresses thereto during said first line interval and for supplying read addresses thereto during said subsequent line interval; and (e) circuit means coupled to said generator means for storing the last address written in said memory means during a memory write operation and for controlling the starting time of at least one subsequent memory read operation in accordance with the stored address.

Claim 7

Video display apparatus as recited in claim 4 wherein: said memory address generator means comprises address counter means having a reset input responsive to a reset signal supplied thereto for placing said counter means in a predetermined initial state corresponding to a given starting address of said memory means; and said circuit means comprises latch means coupled to said counter means for storing said last address written in said memory means during said memory write operation and comparator means coupled to input and output means of said latch means for detecting said starting time of said at least one subsequent memory read operation and supplying said reset signal to said address counter means to initiate the start of said at least one subsequent memory read operation.