Switched capacitor decimator

Claim 2

A switched capacitor decimator circuit having an input node and an output node, comprising: amplifier means having an input and an output, said output of said amplifier means being coupled to said output node, said amplifier means having a characteristic DC offset voltage; a first capacitance (Cint) that is switchably coupled, at a rate equal to a first frequency, between said input and said output of said amplifier means; a second capacitance (Cin) that is coupled between said input node and said input of said amplifier means, wherein a gain G of said switched capacitor decimator circuit is given by nCin/cint, where n is a ratio of said first frequency to a second, lower frequency; and means for DC offset compensating said switched capacitor decimator circuit such that the DC offset voltage of said amplifier means appears at said output node amplified with a gain of unity.

Claim 3

A switched capacitor decimator circuit as set forth in claim 1 wherein Cint is comprised of a first capacitance (Cint1) and a second capacitance (Cint2) that is switchably coupled in parallel with Cint1, and wherein a gain of said switched capacitor decimator circuit is controllably set to one of at least two valves by selectively switching Cint2 in parallel with Cint1.

Claim 4

A switched capacitor decimator circuit as set forth in claim 1 and further including a capacitance coupled between said output of said amplifier means and said input node for suppressing a switching transient of said switched capacitor decimator circuit.

Claim 5

A switched capacitor decimator circuit having an input node and an output node, comprising: amplifier means having an input and an output, said output of said amplifier means being coupled to said output node, said amplifier means having a DC offset voltage; a first capacitance having a first terminal that is switchably coupled between said input node and a reference potential, said first capacitance having a second terminal that is coupled to said input of said amplifier means; a second capacitance that is switchably coupled, at a rate equal to a frequency of a first frequency signal, between said input and said output of said amplifier means, said second capacitance having a first terminal that is switchably coupled to said output of said amplifier means and a second terminal that is coupled to said input of said amplifier means; a third capacitance having a first terminal that is switchably coupled between said input node and the reference potential, said third capacitance having a second terminal that is switchably coupled between the reference potential and said input of said amplifier means; a fourth capacitance having a first terminal that is coupled to said output node and a second terminal that is coupled to said second terminal of said third capacitance; a fifth capacitance that is coupled between said output node and said first terminal of said first capacitance; wherein a gain of said switched capacitor decimator circuit is given by n tines the ratio of said first capacitance to said second capacitance, where n is a ratio of the frequency of said first frequency signal to a second, lower frequency; and a plurality of switching means that are responsive to a first phase of said first frequency signal for, coupling said first terminal of said first capacitance to the reference potential, coupling said first terminal of said second capacitance to said output of said amplifier means; and coupling said first terminal of said third capacitance to said input node while coupling said second terminal of said third capacitance to the reference potential, said switching means being responsive to a second phase of said first frequency signal for, coupling said first terminal of said first capacitance to said input node, uncoupling said first terminal of said second capacitance from said output of said amplifier means, and coupling said first terminal of said third capacitance to the reference potential while coupling said second terminal of said third capacitance to the input of said amplifier means; wherein said plurality of switching means operate to compensate said switched capacitor decimator circuit such that the DC offset voltage of said amplifier means appears at said output node amplified with a gain of unity; wherein said first and second phases of said first frequency signal are applied n times during a sampling interval; and wherein said switched capacitor decimator circuit further comprises switching means coupled across said second capacitance for shorting said output of said amplifier means to said input of said amplifier means at a beginning of the sampling interval.

Claim 6

A switched capacitor decimator circuit having an input node and an output node, comprising: amplifier means having an input and an output, said output of said amplifier means being coupled to said output node, said amplifier means having a DC offset voltage; a first capacitance having a first terminal that is switchably coupled between said input node and a reference potential, said first capacitance having a second terminal that is coupled to said input of said amplifier means; a second capacitance that is switchably coupled, at a rate equal to a frequency of a first frequency signal, between said input and said output of said amplifier means, said second capacitance having a first terminal that is switchably coupled to said output of said amplifier means and a second terminal that is coupled to said input of said amplifier means; a third capacitance having a first terminal that is switchably coupled between said input node and the reference potential, said third capacitance having a second terminal that is switchably coupled between the reference potential and said input of said amplifier means; a fourth capacitance having a first terminal that is coupled to said output node and a second terminal that is coupled to said second terminal of said third capacitance; a fifth capacitance that is coupled between said output node and said first terminal of said first capacitance; wherein a gain of said switched capacitor decimator circuit is given by n tines the ratio of said first capacitance to said second capacitance, where n is a ratio of the frequency of said first frequency signal to a second, lower frequency; and a plurality of switching means that are responsive to a first phase of said first frequency signal for, coupling said first terminal of said first capacitance to the reference potential, coupling said first terminal of said second capacitance to said output of said amplifier means; and coupling said first terminal of said third capacitance to said input node while coupling said second terminal of said third capacitance to the reference potential, said switching means being responsive to a second phase of said first frequency signal for, coupling said first terminal of said first capacitance to said input node, uncoupling said first terminal of said second capacitance from said output of said amplifier means, and coupling said first terminal of said third capacitance to the reference potential while coupling said second terminal of said third capacitance to the input of said amplifier means; wherein said plurality of switching means operate to compensate said switched capacitor decimator circuit such that the DC offset voltage of said amplifier means appears at said output node amplified with a gain of unity; wherein said first and second phases of said first frequency signal are applied n times during a sampling interval; and wherein said switched capacitor decimator circuit further comprises switching means coupled across said second capacitance for shorting said output of said amplifier means to said input of said amplifier means at a beginning of the sampling interval.

Claim 7

A switched capacitor decimator circuit as set forth in claim 4 wherein said second capacitance is comprised of a plurality of capacitances that are switchably connected together for controllably varying the gain of said switched capacitor decimator circuit.